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Datorteknik ArithmeticCircuits bild 1 Computer arithmetic Somet things you should know about digital arithmetic: Principles Architecture Design.

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Presentation on theme: "Datorteknik ArithmeticCircuits bild 1 Computer arithmetic Somet things you should know about digital arithmetic: Principles Architecture Design."— Presentation transcript:

1 Datorteknik ArithmeticCircuits bild 1 Computer arithmetic Somet things you should know about digital arithmetic: Principles Architecture Design

2 Datorteknik ArithmeticCircuits bild 2 Multiplication Can be done in one clock cycle but: Very slow Needs a lot of hardware

3 Datorteknik ArithmeticCircuits bild 3 Multiplication Simn CoCi So Si m n Co Ci So n m

4 Datorteknik ArithmeticCircuits bild 4 Multiplication p7p6p5p4p3p2p1p0 a0 a1 a2 a3 b3b2b1b0 a0b3a0b2a0b1a0b0 a1b3a1b2a1b1a1b0 a2b3a2b2a2b1a2b0 a3b3a3b2a3b1a3b0

5 Datorteknik ArithmeticCircuits bild 5 To avoid those costs: Multiplication is usually multiple-cycle For example: Repeated add, shift In the MIPS: “ cycles for mult” Databook s 3.9 Multiply instruction is not implemented in our simulator

6 Datorteknik ArithmeticCircuits bild 6 Division... is even worse.... Multiple cycle Repeated shift - subtract - test Databook... instruction uses 35 cycles Divide instruction is not implemented in our simulator

7 Datorteknik ArithmeticCircuits bild 7 Division can be done by D shifted right n bits When D is negative: –If D is even: D Arithmetic shift right by n –If D is odd: (D + 1) Arithmetic shift right by n D / 2 n

8 Datorteknik ArithmeticCircuits bild 8 Example - 1 / 2 -1 arith. shift right 1: 111 -> 111 result: -1Wrong (-1 + 1) arith. shift right 1: 000 -> 000 result: 0OK

9 Datorteknik ArithmeticCircuits bild 9 In the mips, Multiply and divide uses special hardware (not the ALU) and special registers “HI”, “LO” (not in our simulator)

10 Datorteknik ArithmeticCircuits bild 10 Floating point? Needs its own hardware! Co-processor, usually a separate chip Main (integer) CPU CP1 Floating point CP0 Control

11 Datorteknik ArithmeticCircuits bild 11 So the ALU does ADD SUBTRACT SIMPLE LOGIC Simple logic is fast, but add / sub is slow because of long critical path

12 Datorteknik ArithmeticCircuits bild 12 Add two numbers input bits in each step Sum Carry from step n-1 Full adder A0 B0 S0 Cin Cout

13 Datorteknik ArithmeticCircuits bild 13 The full adder A B Ci S Co =1 &&& A B Ci S Co 2-level logic or:

14 Datorteknik ArithmeticCircuits bild 14 The carry chain A31 B31 S31 A30 B30 S30 A29 B29 S29 A2 B2 S2 A1 B1 S1 A0 B0 S0 Cin Cout

15 Datorteknik ArithmeticCircuits bild 15 Addition A31 B31 S31 A30 B30 S30 A29 B29 S29 A2 B2 S2 A1 B1 S1 A0 B0 S0 0

16 Datorteknik ArithmeticCircuits bild 16 Subtraction A - B ? A + Neg (B) two’s complement A + Not (B) + 1 one’s complement + 1

17 Datorteknik ArithmeticCircuits bild 17 Add and subtract A31 S31 A30 S30 A29 S29 A2 S2 A1 S1 A0 S0 0 -> add 1 -> sub =1 B31 =1 B31 =1 B31 =1 B31 =1 B31 =1 B31 =1 B31

18 Datorteknik ArithmeticCircuits bild 18 Timing analys There are six gates per stage* * Exor are two gate levels There are 32 stages The critical path are 6 * 32 gate delay! (Ripple adder) We must break up that carry chain!

19 Datorteknik ArithmeticCircuits bild 19 Full adder again: S = A xor B xor Ci Co = (A and B) or ((A xor B) and Ci) We define P = A xor B G = A and B And we get S = P xor Ci Co = G or (P and Ci) =1 A B P & A B G Computed quickly!

20 Datorteknik ArithmeticCircuits bild 20 The full adder.... Si = Pi xor Ci-1 Ci = Gi or (Pi and Ci-1) If we could be given all of the Ci at the same time, Si is just one more xor

21 Datorteknik ArithmeticCircuits bild 21 The full adder C0 = G0 or (P0 and Cin) C1 = G1 or (P1 and C0) C1 = G1 or (P1 and (G0 or (P0 and Cin)) C1 = G1 or P1G0 or P1P0Cin in the K:th position: Ck = Gk or Gk-1Pk or....PkPk-1....P0Cin Wide or Wide and

22 Datorteknik ArithmeticCircuits bild 22 The carry lookahead adder P / G generator (two level logic) Carry generator (two level logic) Final add (exor) A 32 B G P C S Cin

23 Datorteknik ArithmeticCircuits bild 23 At the worst... An N-input AND (OR) has delay lg2 (N) * 2-input delay:

24 Datorteknik ArithmeticCircuits bild 24 The combination of carry lookahead and ripple carry

25 Datorteknik ArithmeticCircuits bild 25 The carry skip adder Full adder & ≥1 & & C0 C4 C8 C12 P4,7 P12,15P8,11 P0,3 G12,15 G8,11 G4,7 G0,3 - If the full adder in step n generates a carry, it will be correct independent of carry in. - A carry generated in step n is propagated through the and / or gates, not through the adders

26 Datorteknik ArithmeticCircuits bild 26 The carry select adder C0 Full adder A B A B A B A B A B A B A B & ≥1 & S SS S

27 Datorteknik ArithmeticCircuits bild 27 Asymptotic time and space requirements Time Space Ripple carry O(n) O(n) Carry lookahead O(log n) O(n log n) Carry skip O(sqrt n) O(n) Carry select O(sqrt n) O(n)


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