Presentation is loading. Please wait.

Presentation is loading. Please wait.

Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going.

Similar presentations


Presentation on theme: "Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going."— Presentation transcript:

1 Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going to study some interesting combinational and sequential blocks, including  Arithmetic circuits: Adders and Subtractor  Counters  Shift Registers Also, we are going to discuss how computer represents floating- point numbers  float and double in C langauge The last topics to discuss are Memory and Logic Arrays 1

2 Arithmetic Circuits Computers are able to perform various arithmetic operations such as addition, subtraction, comparison, shift, multiplication, and division  Arithmetic circuits are the central building blocks of computers (CPUs) We are going to study hardware implementations of these operations Let’s start with adder Addition is one of most common operations in computer 2

3 1-bit Half Adder Let’s first consider how to implement an 1-bit adder Half adder  2 inputs: A and B  2 outputs: S (Sum) and C out (Carry) 3 ABS(um)C(arry) A B Sum Carry

4 1-bit Full Adder Half adder lacks a C in input to accept C out of the previous column Full adder  3 inputs: A, B, C in  2 outputs: S, C out 4 CinABS(um)C out

5 1-bit Full Adder 5 CinABS(um)C out Cin AB Cin AB Cin AB or Slide from Prof. Sean Lee, Georgia Tech Sum C out

6 1-bit Full Adder Schematic 6 A B C in C out S Half Adder Slide from Prof. Sean Lee, Georgia Tech

7 Multi-bit Adder It seems that an 1-bit adder is doing not much of work How to build a multi-bit adder?  N-bit adder sums two N-bit inputs (A and B), and C in (carry-in) Three common CPA implementations  Ripple-carry adders (slow)  Carry-lookahead adders (fast)  Prefix adders (faster) It is commonly called carry propagate adders (CPAs) because the carry-out of one bit propagates into the next bit 7

8 Ripple-Carry Adder The simplest way to build an N-bit CPA is to chain 1- bit adders together  Carry ripples through entire chain 8 Example: 32-bit Ripple Carry Adder

9 4-bit Ripple-Carry Adder 9 Full Adder AB Cin Cout S S0 A0B0 Full Adder AB Cin Cout S S1 A1B1 Full Adder AB Cin Cout S S2 A2B2 Full Adder AB Cin Cout S S3 A3B3 Carry S0 Modified from Prof Sean Lee’s Slide, Georgia Tech A B C in S C out

10 Delay of Ripple Carry Adder 10 S0 A0B0 Carry Cin 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR Slide from Prof. Sean Lee, Georgia Tech

11 Delay of Ripple Carry Adder 11 1 st Stage Critical Path = 3-gate delay = D XOR +D AND +D OR 2 nd Stage Critical Path = 2-gate delay = D AND +D OR (Assume that inputs are applied at the same time) S0 A0B0 Cin S1 A1B1 Slide from Prof. Sean Lee, Georgia Tech

12 Delay of Ripple Carry Adder 12 Critical path delay of a 4-bit ripple carry adder D XOR + 4 (D AND +D OR ) : 9-gate delay Critical path delay of an N-bit ripple carry adder  2(N-1)+3 = (2N+1) - gate delay S0 A0B0 Cin S1 A1B1 S2 A2B2 S3 A3B3 Carry Modified from Prof Sean Lee’s Slide, Georgia Tech

13 Ripple-Carry Adder Delay Ripple-carry adder has disadvantage of being slow when N is large  The delay of an N-bit ripple-carry adder is roughly t ripple = N t FA (t FA is the delay of a full adder) A faster adder needs to address the serial propagation of the carry bit 13

14 Carry-Lookahead Adder The fundamental reason that large ripple-carry adders are slow is that the carry signals must propagate through every bit in the adder A carry-lookahead adder (CLA) is another type of CPA that solves this problem.  It divides the adder into blocks and provides circuitry to quickly determine the carry-out of a block as soon as the carry-in is known 14

15 Carry-Lookahead Adder Compute the carry-out (C out ) for an N-bit block  Compute generate (G) and propagate (P) signals for columns and then an N-bit block  A column (bit i) can produce a carry-out by either generating a carry- out or propagating a carry-in to the carry-out Generate (G i ) and Propagate (P i ) signals for each column  A column will generate a carry-out if both A i and B i are 1 G i = A i B i  A column will propagate a carry-in to the carry-out if either A i or B i is 1 P i = A i + B i Express the carry-out of a column (C i ) in terms of P i and G i C i = A i B i + (A i + B i )C i-1 = G i + P i C i-1 15

16 Carry Generate & Propagate 16 What do these equations mean? Let’s think about these equations for a moment Modified from Prof H.H.Lee’s Slide, Georgia Tech g i = A i B i p i = A i + B i C i = A i B i + (A i + B i ) C i-1 C i = g i + p i C i-1 C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1

17 Carry Generate & Propagate A 4-bit block will generate a carry-out if column 3 generates ( g 3 ) a carry or if column 3 propagates ( p 3 ) a carry that was generated or propagated in a previous column G 3:0 = g 3 + p 3 (g 2 + p 2 (g 1 + p 1 g 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 A 4-bit block will propagate a carry-in to the carry-out if all of the columns propagate the carry P 3:0 = p 3 p 2 p 1 p 0 We compute the carry-out of the 4-bit block (C i ) as C i = G i:j + P i:j C j-1 17

18 4-bit CLA 18 Carry Lookahead Logic g1p1 A1B1 S1 C0 g2p2 A2B2 S2 C1 g3p3 A3B3 S3 C2 g0p0 A0B0 S0 C -1 C3 Slide from Prof. Sean Lee, Georgia Tech

19 A CLA Implementation 19 Carry Lookahead Logic C3 A0B0S0A1B1S1 C -1 A2B2S2A3B3 S3 Only 3 gate delay for each Carry C i = D AND + 2*D OR Slide from Prof. Sean Lee, Georgia Tech C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1 g i = A i B i p i = A i + B i p 3 p 2 p 1 p 0 C -1 p 3 p 2 p 1 g 0 p 3 p 2 g 1

20 32-bit CLA with 4-bit blocks 20 It shows a path to C3 only C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1 C i = G i:j + P i:j C j-1 G 3:0 = g 3 + p 3 (g 2 + p 2 (g 1 + p 1 g 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 P 3:0 = p 3 p 2 p 1 p 0 An implementation in our book: each block contains a 4-bit RCA and carry-lookahead logic

21 CLA Delay The delay of an N-bit CLA with k-bit blocks is roughly: t CLA = t pg + t pg_block + (N/k – 1)t AND_OR + kt FA where  t pg is the delay of the column generate and propagate gates  t pg_block is the delay of the block generate and propagate gates  t AND_OR is the delay from C in to C out of the final AND/OR gate 21 t pg t pg_block t AND_OR

22 Adder Delay Comparisons Compare the delay of 32-bit ripple-carry adder and CLA  The CLA has 4-bit blocks  Assume that each two-input gate delay is 100 ps  Assume that a full adder delay is 300 ps t ripple = Nt FA = 32(300 ps) = 9.6 ns t CLA = t pg + t pg_block + (N/k – 1)t AND_OR + kt FA = [ (7) (300)] ps = 3.3 ns 22

23 Verilog-HDL Representation 23 module adder #(parameter N = 8) (input [N-1:0] a, b, input cin, output [N-1:0] s, output cout); assign {cout, s} = a + b + cin; endmodule

24 Then, When to Use What? We have discussed 3 kinds of CPA  Ripple-carry adder  Carry-lookahead adder  Prefix adder (see backup slides) Faster adders require more hardware and therefore they are more expensive and power-hungry So, depending on your speed requirement, you can choose the right one If you use HDL to describe an adder, the CAD tools will generate appropriate logic considering your speed requirement 24

25 25 Backup Slides

26 An Implementation of CLA 26 A0B0S0A1B1S1A2B2S2A3B3 S3  Carry delay is 4*D AND + 2*D OR for C 3  Reuse some gate output results in little improvement C -1 Slide from Prof. Sean Lee, Georgia Tech C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1 g i = A i B i p i = A i + B i p 0 C -1 p 2 p 1 p 0 C -1 p 1 p 0 C -1 p 3 p 2 p 1 p 0 C -1

27 Prefix Adder Computes generate and propagate signals for all of the columns (!) to perform addition even faster Computes G and P for 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the generate and propagate signals are known for each column  Then, the prefix adder has log 2 N stages The strategy is to compute the carry in (C i-1 ) for each of the columns as fast as possible and then to compute the sum: S i = (A i  B i )  C i-1 27

28 Prefix Adder A carry is generated by being either generated in a column or propagated from a previous column Define column -1 to hold C in, so G -1 = C in, P -1 = 0 Then, C i-1 = G i-1:-1 because there will be a carry out of column i-1 if the block spanning columns i-1 through -1 generates a carry Thus, we can rewrite the sum equation as: S i = (A i  B i )  G i-1:-1 28

29 Prefix Adder The generate and propagate signals for a block spanning bits i:j are G i:j = G i:k  P i:k G k-1:j P i:j = P i:k P k-1:j These signals are called the prefixes because they must be precomputed before the final sum computation can complete In words, these prefixes describe that  A block will generate a carry if the upper part (i:k) generates a carry or the upper part propagates a carry generated in the lower part (k-1:j)  A block will propagate a carry if both the upper and lower parts propagate the carry. 29

30 4-bit Prefix Adder 30 B3B3 B2B2 B1B1 B0B0 A3A3 A2A2 A1A1 A0A0 C in G -1 = C in, P -1 = 0 P 2, G 2 P 1, G 1 P 0, G 0 P -1, G -1 P i = A i B i, G i = A i + B i P 0:-1, G 0:-1 P 2:1, G 2:1 P 2:1 = P 2 P 1, G 2:1 = G 2 + P 2 G 1 P 0:-1 = P 0 P -1, G 0:-1 = G 0 + P 0 G -1 S3S3 S2S2 S1S1 S0S0 S 3 = A 3 B 3 G 2:-1 S 2 = A 2 B 2 G 1:-1 S 1 = A 1 B 1 G 0:-1 S 0 = A 0 B 0 G P 2:-1, G 2:-1 P 2:-1 = P 2:1 P 0:-1, G 2:-1 = G 2:1 + P 2:1 G 0:-1 P 1:-1, G 1:-1 P 1:-1 = P 1 P 0:-1, G 1:-1 = G 1 + P 1 G 0:-1 C -1 = G -1 C 0 = G 0:-1 C 1 = G 1:-1 C 2 = G 2:-1 Remember that P 2:-1 is always “0” since P -1 = 0, but intermediate propagate signals (P 1:-1, P 0:-1, P 2:1 ) are used for calculating subsequent generate signals

31 16-bit Prefix Adder 31 G -1 = C in, P -1 = 0

32 Prefix Adder Delay The delay of an N-bit prefix adder is: t PA = t pg + log 2 N(t pg_prefix ) + t XOR where  t pg is the delay of the column generate and propagate gates  t pg_prefix is the delay of the black prefix cell 32


Download ppt "Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going."

Similar presentations


Ads by Google