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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic January, 2003

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 2 A Generic Digital Processor

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 3 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 4 An Intel Microprocessor Itanium has 6 integer execution units like this

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 5 Bit-Sliced Design

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 6 Bit-Sliced Datapath

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 7 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 8 Adders

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 9 Full-Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 10 The Binary Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 11 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A B Note that we will be sometimes using an alternate definition for

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 12 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 13 Complimentary Static CMOS Full Adder 28 Transistors

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 14 Inversion Property

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 15 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 16 A Better Structure: The Mirror Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 17 Mirror Adder Stick Diagram

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 18 The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 19 Transmission Gate Full Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 20 Manchester Carry Chain

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 21 Manchester Carry Chain

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 22 Manchester Carry Chain Stick Diagram

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 23 Carry-Bypass Adder Also called Carry-Skip

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 24 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 25 Carry Ripple versus Carry Bypass

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 26 Carry-Select Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 27 Carry Select Adder: Critical Path

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 28 Linear Carry Select

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 29 Square Root Carry Select

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 30 Adder Delays - Comparison

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 31 LookAhead - Basic Idea

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 32 Look-Ahead: Topology Expanding Lookahead equations: All the way:

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 33 Logarithmic Look-Ahead Adder

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 34 Carry Lookahead Trees Can continue building the tree hierarchically.

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 35 Tree Adders 16-bit radix-2 Kogge-Stone tree

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 36 Tree Adders 16-bit radix-4 Kogge-Stone Tree

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 37 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 38 Tree Adders Brent-Kung Tree

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 39 Example: Domino Adder PropagateGenerate

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 40 Example: Domino Adder PropagateGenerate

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 41 Example: Domino Sum

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 42 Multipliers

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 43 The Binary Multiplication

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 44 The Binary Multiplication

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 45 The Array Multiplier

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 46 The MxN Array Multiplier — Critical Path Critical Path 1 & 2

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 47 Carry-Save Multiplier

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 48 Multiplier Floorplan

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 49 Wallace-Tree Multiplier

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 50 Wallace-Tree Multiplier

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 51 Wallace-Tree Multiplier

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 52 Multipliers —Summary

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 53 Shifters

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 54 The Binary Shifter

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 55 The Barrel Shifter Area Dominated by Wiring

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 56 4x4 barrel shifter Width barrel ~ 2 p m M

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 57 Logarithmic Shifter

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EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 58 A 3 A 2 A 1 A 0 Out3 Out2 Out1 Out0 0-7 bit Logarithmic Shifter

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