2 Two-Bit Comparator A B C D LT EQ GT 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 LT EQ GTA B < C D A B = C D A B > C DABCDN1N2block diagramandtruth tablewe'll need a 4-variable Karnaugh map for each of the 3 output functions
3 Two-Bit Comparator (cont’d) B C' D' + A C' + A B D'0 01 0DA1 10 1BC1 00 10 0DABC0 10 01 1DA1 0BCA'B'C'D' + A'BC'D + ABCD + AB'CD’A' B' D + A' C + B' C DK-map for LTK-map for EQK-map for GTLT =EQ =GT == (A xnor C) • (B xnor D)
4 Equality Comparator XNOR X Y Z 0 0 1 0 1 0 X 1 0 0 Z 1 1 1 Y XZYZ = X XNOR Y
23 اعمال رياضي باينري: جمع قوانين: مانند جمع دسيمالبا اين تفاوت که1+1 = 10 توليد نقلي0+0 = 0c0 (sum 0 with carry 0)0+1 = 1+0 = 1c01+1 = 0c11+1+1 = 1c1Carry1AugendAddendResult
24 مکمل 2: نمايش اعداد n N* = 2 - N 4 2 = 10000 7 = 0111 sub 2 =7 =1001 = repr. of -7مکمل 2:subExample: Twos complement of 74Example: Twos complement of -72 =-7 =0111 = repr. of 7subShortcut method:Twos complement = bitwise complement + 10111 -> > 1001 (representation of -7)1001 -> > 0111 (representation of 7)
25 جمع و تفريق مکمل 2 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1101 11001 If)carry-in to sign = carry-out (then ignore carryif)carry-in ≠ carry-out(then overflow4- 310100110110001-4+ 3-1110000111111Simpler addition scheme makes twos complement the most commonchoice for integer number systems within digital systems
26 سرريز Overflow Conditions Add two positive numbers to get a negative numberor two negative numbers to get a positive number-1+0-1+0-211110000+1-211110000+111101110-30001-30001+21101+2110100100010-4-41100+300111100+30011-5-5101110110100+40100+4-61010-6101001010101+5+51001100101100110-7+6-71000+6011110000111-8+7-8+75 + 3 = -8= +7
27 سرريز Overflow Conditions 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 5 -7 0 0 1 1 -27Overflow53-8Overflow527No overflow-3-5-8No overflowOverflow when carry in to sign ≠ carry out
28 Half Adder (HA) Add single bits Ai Bi 1 Ai Bi 1 Ai Bi Sum Carry 1 1 1 1AiBi1AiBiSumCarry1111111Sum = Ai Bi + Ai Bi= AiBiCarry = Ai . Bi
30 Full Adder (FA) S = CI xor A xor B A BCI100011110A1BCISCOSA BCI100011110COS = CI xor A xor BCO = B CI + A CI + A B = CI (A + B) + A B
31 Full Adder Using 2 Half Adders A full adder can also be realized with two half adders and an OR gate, since Ci+1 can also be expressed as:Ci+1 = AiBi + (Ai Bi)Ciand Si = (Ai Bi) CiAiBiSiCi+1Ci
32 Example: 4-bit Ripple Carry Adder C4 C3 C2 C1 C A3 A2 A1 A B3 B2 B1 B S3 S2 S1 S0
33 Delay Analysis of Ripple Adder Carry out of a single stage can be implemented in 2 gate delays after CI is ready.For a 16 bit adder, the 16th bit carry is generated after about 16 * 2 = 32 gate delays.The sum bit takes one additional gate delay to generate the sum of the 16th bit after 15th bit carry~ 15 * = 31 gate delaysTakes too long - need to investigate FASTER adders!
35 Carry Lookahead Adder Carry Generate Carry Propagate Gi = Ai Bi must generate carry when A = B = 1Carry PropagatePi = Ai xor Bi carry-in will equal carry-out hereSum and Carry can be reexpressed in terms of generate/propagate:Si = Ai xor Bi xor Ci = Pi xor CiCi+1 = Ai Bi + Ai Ci + Bi Ci= Ai Bi + Ci (Ai + Bi)= Ai Bi + Ci (Ai xor Bi)= Gi + Ci Pi
36 Carry Lookahead AdderC1 = G0 + P0 C0C2 = G1 + P1 C1= G1 + P1 G0 + P1 P0 C0C3 = G2 + P2 C2= G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0C4 = G3 + P3 C3= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0Each of the carry equations can be implemented in a two-level logic networkVariables are the adder inputs and carry in to stage 0!
37 CLA Increasingly complex logic Ai Pi Bi Si Ci Gi @0 @1 @0 @t+1 @t @1
38 Delay Analysis of CLA Ci’s are generated independent of N BCS@21@3A1BS@4C2@34 stageadderA2BS@4C3@3A3BS@4C4@3final sum andcarryNOTE HOWEVER THIS ASSUMES ALL GATE DELAYS ARE SAMENot true, delays depand on fan-ins and fan-out
43 Overflow Overflow can occur ONLY when both numbers have the same sign. This condition can be detected when the carry out (Cn) is different than the carry at the previous position (Cn-1).
44 The Overflow problem in Signed-2’s Complement (cont.) Example 1: M=6510 and N=6510 (In an 8-bit 2’s complement system).M = N =M+N = with Cn=0. (clearly wrong!)Bring Cn as the MSB to get (13010) which is correct, but requires 9-bits overflow occurs.Example 2: M=-6510 and N=-6510M = N =M+N = with Cn=1. (wrong again!)Bring Cn as the MSB to get (-13010) which is correct, but also requires 9-bits overflow occurs.
45 Overflow Detection in Signed-2’s Complement Cn-1CnCn-bit Adder/SubtractorC =1 indicates overflow condition when adding/subtr. unsigned numbers.V=1 indicates overflow condition when adding/subtr. signed-2’s complement numbers
52 اعداد در مبناهاي مختلفAdd 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)
53 BCD Adder Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X) A B 3B3A2B2A1B1ABCOFACICOFACICOFACICOFACICinSSSS11XXA11X1XA2COFACICOFACISSCoutS3S2S1SAdd 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)
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