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Adder Circuits IEP on Synthesis of Digital Design 2007 1 Adder Circuits S. Sundar Kumar Iyer.

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Presentation on theme: "Adder Circuits IEP on Synthesis of Digital Design 2007 1 Adder Circuits S. Sundar Kumar Iyer."— Presentation transcript:

1 Adder Circuits IEP on Synthesis of Digital Design 2007 1 Adder Circuits S. Sundar Kumar Iyer

2 Adder Circuits IEP on Synthesis of Digital Design 2007 2 Acknowledgement  Slides taken from http://bwrc.eecs.berkeley.edu/IcBook/index.htm http://bwrc.eecs.berkeley.edu/IcBook/index.htm which is the web-site of “Digital Integrated Circuit – A Design Perspective” by Rabaey, Chandrakasan, Nicolic

3 Adder Circuits IEP on Synthesis of Digital Design 2007 3 Outline  Background / Basics of Adders  Ripple Carry Adder

4 Adder Circuits IEP on Synthesis of Digital Design 2007 4 A Generic Digital Processor

5 Adder Circuits IEP on Synthesis of Digital Design 2007 5 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

6 Adder Circuits IEP on Synthesis of Digital Design 2007 6 Bit-Sliced Design

7 Adder Circuits IEP on Synthesis of Digital Design 2007 7 Bit-Sliced Datapath

8 Adder Circuits IEP on Synthesis of Digital Design 2007 8 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

9 Adder Circuits IEP on Synthesis of Digital Design 2007 9 Full-Adder

10 Adder Circuits IEP on Synthesis of Digital Design 2007 10 The Binary Adder

11 Adder Circuits IEP on Synthesis of Digital Design 2007 11 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for

12 Adder Circuits IEP on Synthesis of Digital Design 2007 12 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

13 Adder Circuits IEP on Synthesis of Digital Design 2007 13 Complimentary Static CMOS Full Adder 28 Transistors

14 Adder Circuits IEP on Synthesis of Digital Design 2007 14 Inversion Property

15 Adder Circuits IEP on Synthesis of Digital Design 2007 15 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

16 Adder Circuits IEP on Synthesis of Digital Design 2007 16 A Better Structure: The Mirror Adder

17 Adder Circuits IEP on Synthesis of Digital Design 2007 17 Mirror Adder Stick Diagram

18 Adder Circuits IEP on Synthesis of Digital Design 2007 18 The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

19 Adder Circuits IEP on Synthesis of Digital Design 2007 19 Transmission Gate Full Adder

20 Adder Circuits IEP on Synthesis of Digital Design 2007 20 Manchester Carry Chain

21 Adder Circuits IEP on Synthesis of Digital Design 2007 21 Manchester Carry Chain

22 Adder Circuits IEP on Synthesis of Digital Design 2007 22 Manchester Carry Chain Stick Diagram

23 Adder Circuits IEP on Synthesis of Digital Design 2007 23 Carry-Bypass Adder Also called Carry-Skip

24 Adder Circuits IEP on Synthesis of Digital Design 2007 24 Carry-Bypass Adder (cont.) t adder = t setup + Mt carry + (N/M-1)t bypass + (M-1)t carry + t sum

25 Adder Circuits IEP on Synthesis of Digital Design 2007 25 Carry Ripple versus Carry Bypass

26 Adder Circuits IEP on Synthesis of Digital Design 2007 26 Carry-Select Adder

27 Adder Circuits IEP on Synthesis of Digital Design 2007 27 Carry Select Adder: Critical Path

28 Adder Circuits IEP on Synthesis of Digital Design 2007 28 Linear Carry Select

29 Adder Circuits IEP on Synthesis of Digital Design 2007 29 Square Root Carry Select

30 Adder Circuits IEP on Synthesis of Digital Design 2007 30 Adder Delays - Comparison

31 Adder Circuits IEP on Synthesis of Digital Design 2007 31 LookAhead - Basic Idea

32 Adder Circuits IEP on Synthesis of Digital Design 2007 32 Look-Ahead: Topology Expanding Lookahead equations: All the way:

33 Adder Circuits IEP on Synthesis of Digital Design 2007 33 Logarithmic Look-Ahead Adder

34 Adder Circuits IEP on Synthesis of Digital Design 2007 34 Carry Lookahead Trees Can continue building the tree hierarchically.

35 Adder Circuits IEP on Synthesis of Digital Design 2007 35 Tree Adders 16-bit radix-2 Kogge-Stone tree

36 Adder Circuits IEP on Synthesis of Digital Design 2007 36 Tree Adders 16-bit radix-4 Kogge-Stone Tree

37 Adder Circuits IEP on Synthesis of Digital Design 2007 37 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

38 Adder Circuits IEP on Synthesis of Digital Design 2007 38 Tree Adders Brent-Kung Tree

39 Adder Circuits IEP on Synthesis of Digital Design 2007 39 Example: Domino Adder PropagateGenerate

40 Adder Circuits IEP on Synthesis of Digital Design 2007 40 Example: Domino Adder PropagateGenerate

41 Adder Circuits IEP on Synthesis of Digital Design 2007 41 Example: Domino Sum


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