Download presentation

Presentation is loading. Please wait.

1
EE141 Adder Circuits S. Sundar Kumar Iyer

2
Acknowledgement Slides taken from which is the web-site of “Digital Integrated Circuit – A Design Perspective” by Rabaey, Chandrakasan, Nicolic

3
Outline Background / Basics of Adders Ripple Carry Adder

4
**A Generic Digital Processor**

5
**Building Blocks for Digital Architectures**

Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

6
Bit-Sliced Design

7
Bit-Sliced Datapath

8
**Itanium Integer Datapath**

Fetzer, Orton, ISSCC’02

9
Full-Adder

10
The Binary Adder

11
**Express Sum and Carry as a function of P, G, D**

Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A Å B Delete = A B Can also derive expressions for S and C based on D and P o Note that we will be sometimes using an alternate definition for Propagate (P) = A + B

12
**The Ripple-Carry Adder**

Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit

13
**Complimentary Static CMOS Full Adder**

28 Transistors

14
Inversion Property

15
**Minimize Critical Path by Reducing Inverting Stages**

Exploit Inversion Property

16
**A Better Structure: The Mirror Adder**

17
Mirror Adder Stick Diagram

18
The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . The transistors connected to Ci are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

19
**Transmission Gate Full Adder**

20
**Manchester Carry Chain**

21
**Manchester Carry Chain**

22
**Manchester Carry Chain**

Stick Diagram

23
Carry-Bypass Adder Also called Carry-Skip

24
**Carry-Bypass Adder (cont.)**

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

25
**Carry Ripple versus Carry Bypass**

26
Carry-Select Adder

27
**Carry Select Adder: Critical Path**

28
Linear Carry Select

29
**Square Root Carry Select**

30
**Adder Delays - Comparison**

31
LookAhead - Basic Idea

32
Look-Ahead: Topology Expanding Lookahead equations: All the way:

33
**Logarithmic Look-Ahead Adder**

34
Carry Lookahead Trees Can continue building the tree hierarchically.

35
Tree Adders 16-bit radix-2 Kogge-Stone tree

36
Tree Adders 16-bit radix-4 Kogge-Stone Tree

37
Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

38
Tree Adders Brent-Kung Tree

39
Example: Domino Adder Propagate Generate

40
Example: Domino Adder Propagate Generate

41
Example: Domino Sum

Similar presentations

OK

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha.

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on principles of object-oriented programming concepts Ppt on applied operational research notes Ppt on weapons of mass destruction Ppt on power line communication pdf Ppt on product advertising image Ppt on teamviewer download Ppt on forest resources in india Download ppt on community planning for disaster management Ppt on information technology security Ppt on tcp/ip protocol suite presentation