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**Carry Lookahead Homework**

You are required to calculate the performance of a 16-bit Carry lookahead adder similar to the one discussed in class. The design has 2 options assuming ripple carry is used inside each 4-bit cell Carry lookahead is used inside each 4-bit cell Both cases use carry lookahead at predicting 4-bit boundary carries [c4, c8, c12] Draw a table showing the delay of each adder bit i.e. Sum0 - Sum 15; for each case 9/12

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**8-bit carry lookahead adder (4-bit block is also CLA)**

c4= G0 + c0 P0 2nd level carry lookahead a0 b0 a1 b1 a2 b2 a3 b3 3 4 units of delay 6 G0 P0 G1 P1 5 c5= g4 + c4.p4 Delays 9/12

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**8-bit CLA – uses ripple carry inside 4-bit block**

a0 b0 Result0 Result1 Result2 Result3 a1 b1 a2 b2 a3 b3 a4 b4 Result4 Result5 Result6 Result7 a7 b7 a6 b6 a5 b5 2nd level carry lookahead c4 2 2 3 4 5 6 7 4 5 6 7 8 9 10 11 9/12

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Array Multiply HW Refer to slide 31 in your ALU slides – Array multiply Using the cell, Draw the architecture of an 8 x 8 array multiplier showing all connections Calculate all the delays for the multiplier, assume Ripple add architecture. Each adder delay is 2 units, carry in to carry out is 2 and AND gate is 1 unit delay. You need to show the delays throughout the multiplier on your diagram. Give any assumptions made and explain your answer..i.e .how you arrived at the delays (delays are similar to adder delays)

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ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.

ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.

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