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FinFET: a mature multigate MOS technology

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1 FinFET: a mature multigate MOS technology
FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin1, T.M. Chung1, D. Lederer1, A. Dixit2, N. Collaert2, T. Rudenko3, V. Kilchytska3, D. Flandre3 Université catholique de Louvain, 1Microwave and 4Microelectronics Laboratories Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium 2IMEC, Kapeldreef, 75, B-3001 Leuven, Belgium 3ISP, Kiev

2 Growing interest for MuG
Strong limitations - Short Channel Effects - appearing for Single Gate MOS below 50 nm Many technological difficulties to satisfy the ITRS predictions, in terms of leakage current (IOFF), supply voltage, Early voltage, DIBL, cutoff frequency, etc. Multiple-gate MOSFETs (MuG) are considered as serious potential candidates Planar MuG < > Non-planar MuG

3 Planar MuG GAA: First planar DG MOS Isotropic wet etching of BOX
good gate oxide-channel interfaces, channel thickness controlled by highly selective wet etching Need: variable W/L >< GAA (W/L=1) Planar DG built by wafer bonding starting with SG MOS Gate stacks are not built at the same time (dissimetry) Misalignment of top and bottom gates Planar DG built by transfer of a thin Si film above a cavity Both gates are built simultaneously GAA [Colinge, SOI Conf. 90] SON-GAA, ST-M, IEDM’03 DG, CEA-LETI, SOI Conf. 04 Self-aligned DG process, but no DG MOS yet DG, UCL, SPIE 04

4 Non-planar MuG FinFET, Triple gate Omega gate, Pi-Gate FinFET
IMEC, SSE’04 Taiwan Semicon., IEDM’02

5 RF analog factors of merit
Several good published articles investigated the intrinsic behavior of MuG experimentally and through simulations: ION/IOFF, Subthreshold slope, Vth roll-off, DIBL. Analyses focused on RF analog performance – not limited to the channel behavior (impact of parasitics related to the 3-D structure) Year Lmin / node (nm) tox (nm) 5.Lmin Parasitic cap. (fF/µm) fT (GHz) 2005 45 / 80 2.1 100 0.24 140 2006 37 / 70 1.9 170 2007 32 / 65 1.6 200 2009 25 / 50 1.4 280 2012 18 / 35 1.2 400 2015 12 / 25 1.0 700 ITRS

6 Measured MuG FinFET from IMEC Planar DG from UCL
Gate lengths L from 10 µm down to 50 nm Fin width Wfin from 10 µm down to 22 nm Fin height Hfin from 60 to 95 nm Fin spacing (Sfin) from 100 to 350 nm Nitrided gate oxide of 2 nm EOT NiSi salicide Planar DG from UCL SiO2 gate oxide of 30 or 6 nm Si film of 87 nm BOX = 400 nm L from 20 down to 1 µm

7 Non-planar vs. planar MuG
3-D Atlas simulations of SOI MOSFETs Multiple-Gate Devices in static and dynamic regimes Single-, Double-, Triple-, and Pi-Gate MOS L from 200 nm down to 25 nm Hfin = 50 nm Tsi = Wfin = 20 nm Tox = 2 nm Tbox = 150 nm Channel doping = 1015 cm-3 (undoped)

8 Static simulation results
- Roll-off Vth , degradation of S and DIBL for SG for Lg < 100 nm Solution: Reduce Si channel thickness (Vth control), but technological problems in terms of uniformity and increase of Rs and Rd. - Pi-gate present slightly better results, lower SCE - At L = 25 nm, MuG with tSi = Wfin = 20 nm show degradation of their performance

9 Gm/Id: efficiency to convert DC to AC
Intrinsic voltage gain = Gm/Gd = Gm/Id x Id/Gd = Gm/Id x VEA Planar SOI SG and DG FinFETs Measurement results

10 Volume inversion (VI) 100 nm DG MOSFET Undoped DG  and SG - - - Clear interest for DG for channel length < 100 nm VI is not efficient at high Vgo Simulation results

11 Early Voltage vs Wfin and L
FinFETs L = 10 µm Measurement results VEA for FinFET in VI regime is 10 x higher than for FD SOI

12 Intrinsic analog gain Higher intrinsic gain for FinFET of around 20 dB compared to FD SOI MOS

13 Dynamic analysis of MuG
Simulation results At low Vgo, the gmMuG/gmSG and CgsMuG/CgsSG ratios are > 1 At higher Vgo, no improvement on normalized gm for MuG over SG Volume inversion in MuG only efficient at lower Vgo

14 Miller capacitance Cgd
Measured Cgs/Cgd = 3 for 60 nm FinFET Cgs/Cgd: Ratio of Control capacitance of the channel to Parasitic feedback Miller capacitance. MuG devices achieve a higher value of Cgs/Cgd as compared to SG devices

15 3-D parasitic capacitances
Normalized Cgs Higher parasitic capacitances: TG > DG > SG due to more complex 3-D interconnection Main part of the parasitic capacitance is related to fringing field between gate-to-source and gate-to-drain through BOX

16 Cutoff frequency For long L, fT of SG slightly higher due to lower parasitic C compared to MuG At small L, SG device, very high SCE, leading to bad fT value Even MuG devices with L < 40 nm, degradation appears To follow up the ITRS, we have to reduce Wfin or tsi as well as EOT (high-k) Vgo = 500 mV and Vds = 1 V

17 Conclusions – Maturity of FinFETs?
FinFET: very promising technological solution at short term Advantages: - higher technological maturity than planar DG - parasitic capacitances related to the 3-D FinFET structure are only slightly higher than for SG Disadvantages: - reduced mobility for electrons (<110> cristalline orientation) - control of Wfin by etching + gate interface quality - higher source/drain resistances Rs, Rd → reduced gm → lower fT and fmax Rg → reduced fmax Short term technological challenges: gate interface quality, silicidation S/D or Low Schottky Barrier S/D contacts, integration density

18 Acknowledgements UCL clean rooms team Mr. P. Simon for RF measurements
Dr. Jurczak Malgorzata’s group, IMEC SINANO

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