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FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1, T.M. Chung 1, D. Lederer 1, A.

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Presentation on theme: "FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1, T.M. Chung 1, D. Lederer 1, A."— Presentation transcript:

1 FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1, T.M. Chung 1, D. Lederer 1, A. Dixit 2, N. Collaert 2, T. Rudenko 3, V. Kilchytska 3, D. Flandre 3 Université catholique de Louvain, 1 Microwave and 4 Microelectronics Laboratories Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium 2 IMEC, Kapeldreef, 75, B-3001 Leuven, Belgium 3 ISP, Kiev

2 Growing interest for MuG Strong limitations - Short Channel Effects - appearing for Single Gate MOS below 50 nm Many technological difficulties to satisfy the ITRS predictions, in terms of leakage current (I OFF ), supply voltage, Early voltage, DIBL, cutoff frequency, etc. Multiple-gate MOSFETs (MuG) are considered as serious potential candidates Planar MuG Non-planar MuG

3 Planar MuG GAA: First planar DG MOS –Isotropic wet etching of BOX –good gate oxide-channel interfaces, channel thickness controlled by highly selective wet etching –Need: variable W/L >< GAA (W/L=1) Planar DG built by wafer bonding starting with SG MOS –Gate stacks are not built at the same time (dissimetry) –Misalignment of top and bottom gates Planar DG built by transfer of a thin Si film above a cavity –Both gates are built simultaneously –Misalignment of top and bottom gates GAA [Colinge, SOI Conf. 90] SON-GAA, ST-M, IEDM03DG, CEA-LETI, SOI Conf. 04 DG, UCL, SPIE 04 Self-aligned DG process, but no DG MOS yet

4 Non-planar MuG FinFET FinFET, Triple gate Omega gate, Pi-Gate IMEC, SSE04 Taiwan Semicon., IEDM02

5 RF analog factors of merit Several good published articles investigated the intrinsic behavior of MuG experimentally and through simulations: I ON /I OFF, Subthreshold slope, V th roll-off, DIBL. Analyses focused on RF analog performance – not limited to the channel behavior (impact of parasitics related to the 3-D structure) YearL min / node (nm) t ox (nm)g m /g 5.L min Parasitic cap. (fF/µm) f T (GHz) / / / / / / ITRS

6 Measured MuG FinFET from IMEC Gate lengths L from 10 µm down to 50 nm Fin width W fin from 10 µm down to 22 nm Fin height H fin from 60 to 95 nm Fin spacing (S fin ) from 100 to 350 nm Nitrided gate oxide of 2 nm EOT NiSi salicide Planar DG from UCL SiO 2 gate oxide of 30 or 6 nm Si film of 87 nm BOX = 400 nm L from 20 down to 1 µm

7 3-D Atlas simulations of SOI MOSFETs Multiple-Gate Devices in static and dynamic regimes Non-planar vs. planar MuG Single-, Double-, Triple-, and Pi-Gate MOS L from 200 nm down to 25 nm H fin = 50 nm T si = W fin = 20 nm T ox = 2 nm T box = 150 nm Channel doping = cm -3 (undoped)

8 Static simulation results - Roll-off V th, degradation of S and DIBL for SG for Lg < 100 nm Solution: Reduce Si channel thickness (V th control), but technological problems in terms of uniformity and increase of R s and R d. - Pi-gate present slightly better results, lower SCE - At L = 25 nm, MuG with t Si = W fin = 20 nm show degradation of their performance

9 G m /I d : efficiency to convert DC to AC Intrinsic voltage gain = G m /G d = G m /I d x I d /G d = G m /I d x V EA FinFETs Planar SOI SG and DG Measurement results

10 Volume inversion (VI) Simulation results Clear interest for DG for channel length < 100 nm VI is not efficient at high V go Undoped DG and SG nm DG MOSFET

11 Early Voltage vs W fin and L FinFETs Measurement results L = 10 µm V EA for FinFET in VI regime is 10 x higher than for FD SOI

12 Intrinsic analog gain Higher intrinsic gain for FinFET of around 20 dB compared to FD SOI MOS

13 Dynamic analysis of MuG Simulation results At low V go, the g mMuG /g mSG and Cgs MuG /Cgs SG ratios are > 1 At higher V go, no improvement on normalized g m for MuG over SG Volume inversion in MuG only efficient at lower V go

14 Miller capacitance C gd C gs /C gd : Ratio of Control capacitance of the channel to Parasitic feedback Miller capacitance. MuG devices achieve a higher value of C gs /C gd as compared to SG devices Measured C gs /C gd = 3 for 60 nm FinFET

15 3-D parasitic capacitances Higher parasitic capacitances: TG > DG > SG due to more complex 3-D interconnection Main part of the parasitic capacitance is related to fringing field between gate-to-source and gate-to-drain through BOX Normalized C gs

16 Cutoff frequency - For long L, f T of SG slightly higher due to lower parasitic C compared to MuG - At small L, SG device, very high SCE, leading to bad f T value - Even MuG devices with L < 40 nm, degradation appears - To follow up the ITRS, we have to reduce W fin or t si as well as EOT (high-k) V go = 500 mV and V ds = 1 V

17 FinFET: very promising technological solution at short term Advantages: - higher technological maturity than planar DG - parasitic capacitances related to the 3-D FinFET structure are only slightly higher than for SG Disadvantages:- reduced mobility for electrons ( cristalline orientation) - control of W fin by etching + gate interface quality - higher source/drain resistances Conclusions – Maturity of FinFETs? R s, R d reduced g m lower f T and f max R g reduced f max Short term technological challenges: gate interface quality, silicidation S/D or Low Schottky Barrier S/D contacts, integration density

18 Acknowledgements UCL clean rooms team Mr. P. Simon for RF measurements Dr. Jurczak Malgorzatas group, IMEC SINANO


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