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MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

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Presentation on theme: "MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM."— Presentation transcript:

1 MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM Microprocessor ASSP Controller Chip Modem Chip X Combinational Sequential REGREG MEMORY DECODER MUXMUX Simple Basic FA A B Ci S Co Complex Static Dynamic Parallel Connection Series Connection p n n + + MOSFET Bipolar Diode np n+ p DEVICE WORLD OF DIGITAL IC Copy Right August 2002 Maitham Shams Dept of Electronics Carleton University Ottawa, CANADA

2 The MOSFET © Maitham Shams 2002 n+ Gate Oxide Source Drain Body p-substrate Gate 2 Thin Oxide (S i O 2 ) ) Polycrystalline Silicon or Polysilicon (conductor) Lightly doped Bulk Contact Field Oxide p+ Channel stop implant or field implant 2 Thick Oxide (S i O 2 ) Heavily doped by implantation or diffusion For insulating devices from each other Metal-Oxide-Semiconductor Field-Effect Transistor Unipolar and symmetric device with four terminals of Gate, Source, Drain, and Body NMOS: n-type Source and Drain, p-type Body connected to ground (GND) PMOS: p-type Source and Drain, n-type Body connected to power supply (V DD )

3 CMOS Technology © Maitham Shams 2002 PMOSNMOS p+ n+ p-substrate p+ contact cut Polysilicon n-well Metal Gate oxide Complementary Metal Oxide Silicon Technology combines NMOS and PMOS Mainstream IC Technology in Foreseeable Future High Integration Density Simple Processing Steps Low Power Consumption Adequate Speed High Reliability

4 MOSFET Types and Symbols © Maitham Shams 2002 D G S D G S D G S B AnalogDigital With non standard substrate connection Enhancement PMOS Depletion PMOS I DS V GS +V Tp 0 I DS V GS - V Tp 0 AnalogDigital With non standard substrate connection Enhancement NMOS Depletion NMOS I DS V GS + V Tn 0 0 I DS V GS -V Tn Enhancement mode transistors are normally OFF (non-conducting with zero bias) Depletion mode transistors are normally ON (conduct with zero bias) Most CMOS ICs use Enhancement type MOS

5 © Maitham Shams 2002 Accumulation Gate Body V GS + - n+ Source Drain p-type substrate + _ + _ + _ + _ + _ + _ (B) (S)(G) (D) Depletion Cut-off (no current) MOS Theory of Operation G Depletion layer n+ p-type substrate _ DS B _____

6 MOS Operation (Triode Mode) © Maitham Shams 2002 Threshold voltage, V T, is the potential difference between gate and source, V GS, just enough to invert the channel and let the current flow Inversion Layer (n-type Channel) G Depletion Layer n+ p-type substrate DS _ B ___________ Inversion Current Flow In triode (also called linear) mode current flow increases by increasing V GS and V DS

7 MOS Operation (Saturation Mode) © Maitham Shams 2002 Current flow is constant almost independent of V DS Inversion Layer (n-type Channel) Pinch-off G Depletion Layer n+ p-type substrate DS _ B _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ G n+ p-type substrate DS _ B _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Edge of Saturation

8 The Threshold Voltage © Maitham Shams 2002 V T =  ms - 2  F - QBQB C ox - Q SS C ox - QIQI = V T - ideal + V FB Work-function difference between gate material and Si = (  gate -  Si ) = - (E g /2 +  F ) Ideal V T Voltage drop across Depletion region At inversion Voltage drop across oxide (function of V SB ) Implants: to adjust VT by introducing a small doped region at oxide/substrate surface Surface Charge : due to imperfection in the oxide/substrate interface & doping Depletion Layer Charge Band gap energy of Si = (1.16 – 0.704x10 -3 T2T2 T )5)5 Gate-Oxide Capacitance per unit area C OX =  OX t OX Oxide permittivity = 3.5 x F/cm Oxide thickness ~ 20nm (200A)

9 The Threshold Voltage © Maitham Shams 2002 V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) V T0 =  ms - 2  F - Q B0 C OX - Q SS C OX - QIQI Zero-Bias Q B Zero-Bias V T  =  2q  Si N A C OX Body Effect Coefficient Body Effect refers to an increase in absolute value of threshold voltage when body is at lower potential than source in NMOS and higher potential than source in PMOS transistors Doping Density Subthreshold Current is small amount of current that flows through the channel when gate-to-source potential is below threshold voltage

10 MOS I – V Relations © Maitham Shams 2002 I D as a function of V DS  I D as a function of V GS I D (mA) V DS (V) Triode Saturation GS V = 5V V GS = 4V V GS = 3V V GS = 2V V GS = 1V V DS = V GS - V T  ID ID V GS (V) V T Subthreshold Current V DS = 5V Channel Length Modulation Refers to the fact that due to the enlargement of depletion layer on the drain side and, hence, reduction of channel length, I D slightly increases as V DS increases in saturation

11 Simple MOSFET Model © Maitham Shams 2002 V DS > V GS – V T Saturation Square Law: I D = ( V GS - V T ) 2 (1 + V DS ) k’nk’n L W V DS < V GS – V T Linear I D = {( V GS - V T )V DS - k’nk’n L W 2 V DS 2 } W Drain Source L Gate Designers usually change size (usually width) of transistor to get the right amount of current Saturation (ON) and cut-off (OFF) are the more important modes in operation of digital circuits Process transconductance parameter Is electron mobility, about 3 times larger than hole mobility MOS technologies are known by their Feature Length (minimum allowable L)

12 MOS Capacitances © Maitham Shams 2002 c GS, c GD are oxide capacitances between gate and channel on the source and drain sides, respectively c SB and c DB are junction (also called diffusion) capacitances due to reverse-biased diodes G S B D n+ Source Drain p-substrate Gate t ox Body MOS parasitic capacitances govern it’s dynamic behavior MOS capacitances are non- linear functions of voltages across them c GB is a combination of gate-to-channel and channel-to-body capacitances

13 Gate-Oxide MOS Capacitances © Maitham Shams 2002 Average Gate Related Capacitances Operation Region Cut-Off Triode Saturation

14 Junction Capacitance © Maitham Shams 2002 Average value of C j between V H and V L C eq =  Q j /  V D = K eq C j K eq = -  0 m (V H – V L )(1-m) x [(  0 – V H ) 1-m – (  0 – V L ) 1-m ] C j = C j0 (1 – V D /  0 ) m Junction capacitance at zero bias given per unit area Grading coefficient  0.5 for abrupt junction  0.3 for linear junction Junction behaves like a capacitance becomes its charge depends on the voltage across it

15 Non-ideal Behaviour of MOSFET © Maitham Shams 2002  - Power Law for Sub-micron MOS in Saturation I D =  W(V GS – V T ) ,   1.25 Short Channel Effects: Velocity Saturation and Mobility Degradation Threshold variations Parasitic Resistances Subthreshold current Latch up

16 The Threshold Voltage © Maitham Shams 2002 Example: V T0 = 0.75 V,  =  F = -0.6V, V SB = 5V V T = 1.6V > 2V T0


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