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1 Aniket A. Breed/ Dr. Marc Cahay Silicon on Insulator MOSFET Technology: Design and Evolution of the Modern SOI Fully-depleted MOSFETPresented By:Aniket A. Breed/ Dr. Marc CahayDepartment of Electrical and Computer Engineering and Computer Science.Semiconductor Devices Laboratory
2 SOI – The technology of the future. Welcome to the world of Silicon On InsulatorHighlightsReduced junction capacitance.Absence of latchup.Ease in scaling (buried oxide need not be scaled).Compatible with conventional Silicon processing.Sometimes requires fewer steps to fabricate.Reduced leakage.Improvement in the soft error rate.DrawbacksDrain Current Overshoot.Kink effectThickness control (fully depleted operation).Surface states.
3 The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) In layman terms, MOSFET acts like a switch
5 MotivationSilicon-only planar transistors are fast approaching their scaling limit.Short channel effects limiting scaling into sub nanometer regime.Oxide thickness cannot be scaled down further, problems of tunneling.Need to keep Silicon technology as the base technology while innovating future devices; cost is an important factor.Performance and power dissipation need to be improved.Smaller is faster !!
8 What After the Planar MOSFET (Alternative Approaches) Strained Silicon ApproachSilicon-on-Insulator (SOI) ApproachSilicon grown on a layer of relaxed material like SiGe which has a near similar lattice constant as that of Silicon.Strain induced in Silicon results in an improvement in the mobility, hence results in faster devices.Silicon channel layer grown on a layer of oxide.Absence of junction capacitance makes this an attractive option.Low leakage currents and compatible fabrication technology.
9 Classification of SOI MOSFETs Conventional MOSFETPartially depleted SOI MOSFETFully depleted SOI MOSFETSilicon film thickness greater than bulk depletion width for a partially-depleted MOSFET and less than the gate depletion width for a fully-depleted MOSFET.Partially depleted MOSFETs often plagued by KINK effects, fully depleted devices virtually free from such effects.Partially depleted devices can be faster than fully depleted devices under certain operating conditions.
10 Illustration of the “Kink” effect (Partially depleted structures) Partially depleted MOSFETFully depleted MOSFETKink effect is an intricate, yet undesirable phenomenon.
11 Why Multi-Gate SOI MOSFETs ? Higher current drive better performanceProphesized to show higher tolerance to scaling.Better integration feasibility, raised source-drain structure, ease in integration.Larger number of parameters to tailor device performance
12 IBMs FinFET / Double-Gate SOI (Nanoscale Device Research Group) Courtesy: IBM T.J. Watson Research Center, Yorktown Heights, NY
18 Multi-Body Single-Gate Devices Multi-Body Single gate devices an attractive option.Increased current drive using a single gate.Total current nearly equals the current thru one body multiplied by the number of body regions.Fabrication feasibility.Feasible for the Dual-Gate, Tri-Gate and -gate devices.Front-ViewBodyGATETop-View
19 Device Design (A brief Summary) Research InitiativeDevices under investigation completely novel.Only N-channel devices investigated to some extent.Device structural variations and their effect on performance investigated to a minor degree.Microwave performance of the device’s not investigated at all.Modeling Approach at U.C. (Semiconductor Devices Laboratory)Numerical device simulators from SILVACO International and ISE.Extensive 3-D modeling of the four N-channel device structures.P-channel devices to be modeled in succession.RF analysis of the N-channel devices followed by the P-channel devices, extraction of important device parameters.Effect of temperature variation on device performance to be analyzed.
21 Multi-Gate SOI MOSFETs (3-D Views) TriGateDouble Gate/FinFET-GateQuadGate
22 Multi-Gate SOI MOSFETs (2-D Cutplane Views) Double-gate/FinFETTriGate-GateQuadGateNote: Symmetric and Asymmetric devices possible
23 The -Gate Transistor (The Pseudo 4th gate) Physics of operation difficult to understand.Lies somewhere in between a Tri-Gate and a Quadruple-gate device as regards structure.Virtual presence of a back-gate in oxide layer that acts as a pseudo-fourth gate.Presence of the virtual gate prevents electric field lines from the drain from penetrating the channel.Amount of vertical gate polysilicon penetration a design factor.Virtual Back Gate
24 PiGate Transistor (Vertical Gate Penetration Simulation) Baseline device dimensionsGate Length = 50 nmBody Width = 50 nmBody Height = 50 nmChannel Doping = 1x1016 /cm3Source/ Drain Doping = 1x1019 /cm3Oxide Thickness = 2 nmGate Workfunction = 4.6 eVN-type devices considered.50-100nm technology node well developed and has translated into a manufacturable technology.Too shallow or too deep an etch in the oxide necessitates accuracy and also poses stringent fabrication tolerances.Optimum value of 50 nm chosen as the vertical polysilicon penetration depth.
25 Drain-Current (ID - VDS) Characteristics FinFETTriGatePiGateQuadGate
26 Gate (ID - VGS) Characteristics (FinFET and TriGate) FinFET Device CharacteristicsThreshold Voltage = VSubthreshold Slope = 72 mV/decadeOff Current = 70 A/mDIBL = mV/VTriGate Device CharacteristicsThreshold Voltage = VSubthreshold Slope = 84 mV/decadeOff Current = A/mDIBL = mV/VFinFETTriGateOmega-GateQuadruple-Gate
27 Gate (ID - VGS) Characteristics (-gate and Quadruple-gate) -Gate Device CharacteristicsThreshold Voltage = VSubthreshold Slope = mV/decadeOff Current = A/mDIBL = mV/VFinFETTriGateOmega-GateQuadruple-GateQuadruple-Gate DeviceCharacteristicsThreshold Voltage = VSubthreshold Slope = 65 mV/decadeOff Current = 50 A/mDIBL = mV/V
28 Device Structural Variations (Gate Length) FinFETTriGate-GateQuad-GateJ-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp , vol. 49, no. 12, DecDevice DimensionsSubthreshold Slope = mV/decade and lower for switching applications.Number of gates does influence device operation.Fin Width = 50 nmChannel Doping = 1x 1016 /cm3Workfunction = 4.6 eVOxide Thickness = 2 nmA. Breed and K.P. Roenker, pp , International Semiconductor Device Research Symposium, 2001.
29 Device Structural Variations (Channel Doping) FinFETTriGate-GateQuad-GateJ-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp , vol. 49, no. 12, DecDevice DimensionsNear identical behavior in both graphs.Channel doping normally maintained at a low value to minimize effects of scattering.Mobility degradation observed at high values of channel doping.Moderate levels of channel doping could be used.Fin Height/Width = 50 nmGate Length = 50 nmWorkfunction = 4.6 eVOxide Thickness = 2 nmA. Breed and K.P. Roenker, pp , International Semiconductor Device Research Symposium, 2001.
30 Device Structural Variations (Gate Length and Channel Doping) FinFETTriGate-GateQuad-GateDevice DimensionsThreshold voltage decreases with decrease in gate length, short-channel effect seen to exist in these devices.Threshold voltage sensitive to channel doping beyond 1x1016 /cm3.Can we use channel doping to tailor threshold voltage?Fin Height = 50 nmWorkfunction = 4.6 eVOxide Thickness = 2 nmA. Breed and K.P. Roenker, pp , International Semiconductor Device Research Symposium, 2001.
33 Device Design Parameters FinFETTriGate-GateQuad-GateImportant step in device design is not patterning of gate region , but instead it is the patterning of the body width.Ideally increase in the number of gates provides an improvement in performance.Device DimensionsWorkfunction = 4.6 eVOxide thickness = 2 nm
34 Device Design Parameters (..cont.) FinFETTriGate-GateQuad-GateTriGate variation minimal when Fin Width is considered.Ideal Gate Length/ Fin Width ratio for FinFET is 1.3 or higher, for a TriGate is unity or higher, for a -gate it is 0.8 or higher and for a Quadruple-gate it is 0.6 or higher.
35 Effect of Variation in Gate Oxide Thickness FinFETTriGate-GateQuadGateDevice DimensionsChannel Doping = 1x1016 /cm3Fin Width = 50 nmFin Height = 50 nmGate Length = 50 nmGate Workfunction = 4.6 eVThinner oxides with higher dielectric constants could be looked upon as an alternative for either device. (Hints at the need to look into new materials (HfO2, ZrO2) as a substitute for SiO2 in nanoscale devices).A. Breed and K.P. Roenker, pp , International Semiconductor Device Research Symposium, 2001.
36 MOSFET Microwave Performance Silicon-only planar MOSFETs are under consideration.Devices below 200nm gate length are experimental devices.All devices can be optimized for either a larger cut-off frequency or a larger maximum frequency of operation.No strained technology used for MOSFET fabrication.Juin J. Liou and Frank Schwierz, Solid State Electronics, pp , vol. 47, 2003.
37 Current Gain (h21) & Unilateral Power Gain (UMax) Gate Bias = 0.8 VoltsTriGateFinFETTriGateTriGateFinFETFinFETIdentical behavior for the FinFET and TriGate transistors.TriGate performance again superior to the FinFET.Overall device performance better than that of a planar MOSFET !!Legend Current Gain Unilateral Power GainA. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
38 Variation in the Cutoff Frequency (fT) Gate Bias = 0.8 VoltsTriGateTriGateFinFETFinFETSimilar variation of fT with gate bias and frequency exhibited by the FinFET and TriGate transistors.TriGate exhibits a peak value of 51.5 GHz and the FinFET a peak value of 42.2 GHz for the cut-off frequency.TriGate is superior again compared to the FinFET (nearly a 20% improvement)!!Values however less than that reported for an optimized planar RF MOSFET transistor (178 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, , 2003).A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
39 Variation in the Maximum Frequency of Oscillation (FMax) Gate Bias = 0.8 VoltsTriGateTriGateFinFETFinFETSimilar variation of fMax with gate bias and frequency exhibited by the FinFET and TriGate transistors.TriGate exhibits a peak value of 228 GHz and the FinFET a peak value of 183 GHz.TriGate is superior again compared to the FinFET (20% improvement)!!TriGate performs even better than a planar RF transistor (193 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, , 2003) !!A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
40 Conclusions and Future Work Successfully modeled devices in 3-dimensions.Understood device design space and scaling constraints.Undertook a study to understand fabrication tolerances to which every device could be exposed.Both subthreshold and RF performance explored.Future Work:Model p-channel devices, scaling rules could differ.Understand device design in totality given a variation in two or more than two parameters.Investigate their Microwave characteristics.Comparison with n-channel performance for CMOS and BiCMOS incorporation.Understand effects of temperature on device performance.
41 ReferencesA. Breed and K.P. Roenker, “Dual-gate (FinFET) and TriGate MOSFETs: Simulation and design,” Proceedings of the International Semiconductor Device Research Symposium (ISDRS-2003), pp , December 2003.J-T. Park and J-P Colinge, “Multiple-Gate SOI MOSFETs: Device Design Guidelines,” IEEE Transactions on Electron Devices, pp , vol. 49, no. 12, DecAniket Breed and Kenneth P. Roenker, “A Small-signal, RF Simulation Study of Multiple-gate MOSFET Devices,” IEEE Topical Meeting on Silicon Monolithic ICs in RF Systems, Atlanta, GA, Sept