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ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference.

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Presentation on theme: "ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference."— Presentation transcript:

1 ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference

2 Slide 2 Oh No! Is ESD Going to be MuGGed by Yet Another Technology Development?? Dr. MuGFET Give me your ESD!

3 Slide 3 Purpose of this work Introduce the exciting new Multi-Gate Advanced Transistor Technology called the MuGFET and assess its sensitivity to high current ESD behavior Investigate suitable ESD protection methods for this new technology

4 Slide 4 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization –Fully depleted (FD) MuGFETs –Partially depleted (PD) planar FETs –Diodes Failure analysis Protection approaches Conclusions

5 Slide 5 Introduction (1) Classical FET in Bulk Si SD G LW Scaling expected to become difficult due to Short Channel Effects (32nm node and beyond) SiO 2 Si Gate current

6 Slide 6 Introduction (2) Planar FET Device in SOI SD G LW Low junction capacitance speed! Good body control in fully depleted SOI –Requires costly wafers with ultra-thin Si-film SiO 2 Si Gate current

7 Slide 7 Introduction (3) MuGFET Device (or Fin-FET) SD G L SiO 2 Si Gate Channel enclosed by multiple (2, 3, 4) gates Best body control (fully depleted) Suppression of Short Channel Effect Best candidate for continued technology scaling current 2 sides: double-gate 3 sides+top: tri-gate current W

8 Slide 8 Introduction (4) Fully depleted Fin height: 60-88nm (present), 30-40nm (target) Fin width: 50nm (present), 20-30nm (target) Capability to carry ESD current?

9 Slide 9 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization –Fully depleted (FD) MuGFETs –Partially depleted (PD) planar FETs –Diodes Failure analysis Protection approaches Conclusions

10 Slide 10 Test structures SCGS Lg MDR Wgeo L GATE SOURCE DRAIN N+ GATE N+ Planar SOI partially depleted (PD)

11 Slide 11 Test structures CA p+n+ G Gated diode NMOS and Gate diodes available as MuGFET (Fin) and planar SOI types Fin width = 50nm, Fin heights = 88 and 60nm Nickel silicided (no silicide blocking) SD n+ G Nickel Silicide NMOS Buried oxide

12 Slide 12 MuGFET: Grounded Gate NMOS Unprecedented high ESD sensitivity failure instantaneous after breakdown! L pushes out breakdown, but no snapback visible

13 Slide 13 MuGFET: MOS-diode, Gate tied high Gate biasing allows moderate MOS current flow Damage occurs as soon as Vbd of GGNMOS- case is reached non-uniform current flow?

14 Slide 14 Planar PD SOI NFET: Grounded Gate More robust (~2mA/um), reproducible and scalable Very steep on-characteristics L pushes out BD, minor snapback occurs

15 Slide 15 Excellent ESD performance (Fin-type and planar)! Fin-type diodes show less sensitivity to t si Gated Diodes: Fins + Planar (fwd. mode) It2 [mA/um] film thickness t si 88nm60nm Fin-type 500 fins Wsi=25um Planar W=50um

16 Slide 16 Breakdown voltage much higher than for any FET Fin-type diodes in BD do not show premature failure as seen in NFETs resistive ballasting Gated Diodes: Fins + Planar (rev. mode)

17 Slide 17 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization –Fully depleted (FD) MuGFETs –Partially depleted (PD) planar FETs –Diodes Failure analysis Protection approaches Conclusions

18 Slide 18 Failure Analysis: NFETs Planar PD SOI Planar device: uniform damage along gate width –reasonable ESD performance MuGFET: localized damage of neighboring fins –extremely low ESD performance D 80nm ESD S D S G G metal MuGFET No damage

19 Slide 19 Failure Analysis: Diodes (fwd. mode) MuGFET diode: uniform damage of fins –high ESD performance –intrinsic current capability of technology reached MuGFET Planar Planar diode: no failure in silicon ( contact failure?)

20 Slide 20 Failure Analysis: Pulse Width vs. It2 It2 [mA] Tpulse 100ns500ns2500ns Planar NMOS W=50um FinFET diode 500 fins, Wsi=25um Planar diode W=50um Wunsch-Bell-unlike characteristics obtained Planar MOS and FinFET diode: –smaller sensitivity due to more heat sinking

21 Slide 21 Protection Approaches Input protection: dual diode + power clamp approach Output drivers: PD planar device as local clamp provides solution integrated into process Provides both performance and ESD protection FD MuGFET driver PD planar ESD clamp IO pad

22 Slide 22 Conclusions New issues for emerging Multigate technologies: –FinFET MOS: extremely ESD-susceptible Local burn-out of fins –Planar MOS: reasonable ESD hardness Uniform failure signature (even fully silicided!) Available in same process Lower trigger than FinFET local clamp –Gate-biased MOS: Possible as protection, BJT conduction must strictly be avoided –Gated diodes (Fin-type and planar): Diodes needed in any protection scheme FinFET diodes: high ESD currents possible!

23 Gate Dielectric Integrity along the Road Map of CMOS Scaling including Multi-Gate FET, TiN Metal Gate, and HfSiON High-k Gate Dielectric T. Pompl et. al IRPS Conference Infineon Technologies Texas Instruments

24 Slide 24 Investigate: Influences of multi-gate architecture and metal gate on gate dielectric reliability. Demonstrate: Dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric. Purpose

25 Slide 25 fully-depleted triple gate FET with poly-Si gate and SiO 2 (ISSG: 20 Å) fully-depleted triple gate FET with TiN/poly-Si gate and SiO 2 (ISSG: 17 Å) fully-depleted triple gate FET with TiN/poly-Si gate and HfSiON (ALD & post anneal in NH 3, EOT: 10.5 Å, 20% Si, 7-8% N, bottom SiO 2 : 8 Å) TEM Cross Sections of Vertical Silicon Fin

26 Slide 26 State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures. The total length of tested top fin edge is 1.5 m per distribution. High Volume TDDB checks for Weak Spots

27 Slide 27 No major influence on time to breakdown. Important also for SiO 2 channel interface layer of high-k stacks. Orientation of the silicon fin on {100} substrate: SiO 2 grown on silicon side walls with different crystal orientations. Influence of Crystal Orientation

28 Slide 28 SiO 2 & TiN: NFET meets standard reliability performance. HfSiON & TiN: NFET becomes more critical at stress level. Expectations from thickness scaling of poly-Si/SiO 2 towards using 6.5 dec. in time per nm. NFET: Time To Breakdown vs. Gate Voltage 17 Å 10.5 Å

29 Slide 29 SiO 2 & TiN: PFET becomes more critical at stress level. HfSiON & TiN: PFET meets standard reliability performance. PFET: Time To Breakdown vs. Gate Voltage Expectations from thickness scaling of poly-Si/SiO 2 towards using 6.5 dec. in time per nm. 17 Å 10.5 Å

30 Slide 30 NFET: strong dependence of gate leakage on gate voltage needs to be considered for gate dielectric reliability. 1: SiO 2 & poly-Si 2: SiO 2 & TiN PFET becomes equal to NFET 3: HfSiON & TiN NFET gate leakage strongly increased compared to PFET. Due to asymmetry of the high-k stack. Gate Leakage Current vs. Gate Voltage in Inversion Biasing Mode

31 Slide 31 State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures. GOX reliability trend along the road map of CMOS scaling will be dominated by metal gates and high-k dielectrics. The use of metal gate increases gate leakage current density and reduces SiO 2 reliability margin for PFET devices compared to poly- Si/SiO 2. NFET & HfSiON: the extrapolation of dielectric reliability to use conditions needs to consider the strong dependence of gate leakage on gate voltage. PFET & HfSiON: the dielectric reliability meets the level of a standard poly-Si/SiO 2 gate stack of same EOT. Conclusions


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