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MOS – AK Montreux 18/09/06 Institut dÉlectronique du Sud Advances in 1/f noise modeling: 1/f gate tunneling current noise model of ultrathin Oxide MOSFETs UMR 5507 Institut dÉlectronique du Sud – CEM2 UMR 5507, Place E.Bataillon, U.M. II, Montpellier Cedex 5, France. F. MARTINEZ, M.VALENZA

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MOS – AK Montreux 18/09/06 2Introduction Reduction of oxide thickness Increase of gate leakage current Reduction of oxide thickness Increase of gate leakage current Limitation of classical characterization methodsLimitation of classical characterization methods New noise sourcesNew noise sources Low-frequency noise is a very sensitive tool for probing slow oxide traps Low-frequency noise is a very sensitive tool for probing slow oxide traps The gate to channel current noise must be taken into account in the MOSFET noise characterization. The gate to channel current noise must be taken into account in the MOSFET noise characterization. We will show that our 1/f gate noise model can be applied to: We will show that our 1/f gate noise model can be applied to: the characterization of slow oxide trapsthe characterization of slow oxide traps compact noise modeling of MOSFETscompact noise modeling of MOSFETs The off state drain current is dominated by the overlap gate leakage current The off state drain current is dominated by the overlap gate leakage current What about the overlap gate current LF noise ?What about the overlap gate current LF noise ?

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MOS – AK Montreux 18/09/06 3Outline Introduction Introduction Gate current low-frequency noise model and characterization Gate current low-frequency noise model and characterization Drain and gate current LFN Comparison Drain and gate current LFN Comparison Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Conclusion Conclusion

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MOS – AK Montreux 18/09/06 4 Gate current LF Noise Measurements Experimental Set-Up ANALYSER HP89410A A Trans-impedance AMPLIFIER TRANSISTOR V DS V GS

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MOS – AK Montreux 18/09/06 5 Typical Gate Noise PSD 1/f noise level extracted at 1 Hz 1/f noise level extracted at 1 Hz RTS noise observed on Gate current RTS noise observed on Gate current

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MOS – AK Montreux 18/09/06 6 1/f Oxide Trapping noise Model Trapping – Detrapping model (McWhorter) ECEC E Fn EVEV ECEC EVEV EiEi q q qV GB n Poly + SiO 2 p Substrate y EFEF

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MOS – AK Montreux 18/09/06 7 1/f Gate Current Noise Model Fluctuation of the number of filled traps Fluctuation of the Flat Band Voltage Gate Current Fluctuations Power Spectral Density of gate current noise Power Spectral Density of gate current noise V DS = 0 V and homogeneous structure

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MOS – AK Montreux 18/09/06 8 Devices Under Test Nitrided gate dielectric EOT = 1.2 nm Nitrided gate dielectric EOT = 1.2 nm DPN process (Plasma Nitridation)DPN process (Plasma Nitridation) n + Polysilicon Gate (1200 Å) n + Polysilicon Gate (1200 Å) Isolated Devices with Individual Electrodes Isolated Devices with Individual Electrodes Constant Width of 10 µm Constant Width of 10 µm L ranging from 40 nm to 10 µm L ranging from 40 nm to 10 µm nMOS Transistors – 65 nm CMOS Technology

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MOS – AK Montreux 18/09/06 9 1/f Gate Current Noise Model Experimental Validation Slow Oxide trap density extracted from Low frequency gate noise measurements N T (E F ) cm -3 eV -1

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MOS – AK Montreux 18/09/06 10 Impact of Drain Voltage on LF Gate Current Noise There is no low-frequency induced gate noise from channel current noise nMOS W / L = 10 / 0.2 µm

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MOS – AK Montreux 18/09/06 11 Gate RTS Noise Time and Spectral signature of Oxide Single Defect W / L = 10 / 10 µm No RTS noise observed on Drain Current RTS noise observed on Gate Current Single defect characterisation by RTS Gate current noise measurements

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MOS – AK Montreux 18/09/06 12 Gate RTS Noise ECEC EFnEFn EVEV ECEC EVEV EiEi q q qV G B n + Poly SiO 2 p Substrat Y y t EFEF E t0 S.R.H. Statistics Surface Potential Model x t (nm) E T0 (eV) E B (eV) E B (eV) 0 (cm²) 0 (cm²) Typical Characteristics of Nitrogen-related Trap (C. Leyris WoDim 2006)

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MOS – AK Montreux 18/09/06 13Outline Introduction Introduction Gate current low-frequency noise model and characterization Gate current low-frequency noise model and characterization Drain and gate current LFN Comparison Drain and gate current LFN Comparison Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Conclusion Conclusion

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MOS – AK Montreux 18/09/06 14 Comparison of S VFB (f) extracted from Drain and Gate noise measurements The same Flat Band Voltage fluctuations are involved in drain and gate current LF noise nMOS W / L = 10 / 1 µm Drain Current LF noise nMOS W / L = 10 / 1 µm Gate Current LF noise

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MOS – AK Montreux 18/09/06 15 Devices Under Test Nitrided gate dielectric EOT = 12 Ǻ RTN process (Rapid Thermal Nitridation) n+ Poly-silicon Gate (1200 Ǻ) nMOS Transistors Isolated Devices with Individual Electrodes Constant Width of 10 µm L ranging from 0.04 to 10 µm Standard devices Bulk Gate stack Channel engineering Devices parameters Strained devices Si 0.8 Ge 0.2

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MOS – AK Montreux 18/09/06 16 Drain current noise measurements S VG (f) obtained from the drain noise model are independent of the gate biases 1/f behavior is observed An average value of was found around 0.8 Trap density exponentially decreases when moving away from Si/SiON interface* Flat band voltage PSD extracted from drain current noise in strong inversion regime *[JAYARAMAN and SODINI, Trans. Electron Devices, 1990] W/L = 10 µm / 0.34 µm -0.8

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MOS – AK Montreux 18/09/06 17 Gate current noise Gate current noise level at f = 1 Hz for two gate lengths, V DS = 25 mV Data are extracted from the strong inversion regime Levels obtained at f = 1 Hz are in good agreement with the proposed gate noise model

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MOS – AK Montreux 18/09/06 18 Comparison of S Vfb (f) from gate and drain current noise Same values of S Vfb (f) due to the same trapping process are obtained for frequencies below 1 kHz Full shot noise (2qI G ) dominates the gate noise above 1 kHz V DS = 25 mV The same Flat Band Voltage fluctuations are involved in drain and gate current LF noise V GS = 0.95 V 10 x 1 µm² V GS = 0.65 V 10 x 0.34 µm²

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MOS – AK Montreux 18/09/06 19 Strained-channel vs. standard n-MOSFETs Normalized Flat band voltage fluctuation PSD S Vfb x W x L extracted from drain and gate current noise for both strained and standard devices. Good accordance of results achieved for several gate lengths As the same gate stack process was used for both architectures The slow oxide trap densities involved in LFN are not affected by channel engineering V DS = 25 mV V GS = 0.8 V

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MOS – AK Montreux 18/09/06 20 Impact of Gate LFN on Drain LFN W / L = 10 / 10 µm Fluctuation Continuity Equation Drain and Source LFN PSD

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MOS – AK Montreux 18/09/06 21 LF Gate-Source noise model Electrical Modeling of LF Gate Current Noise Noiseless MOSFET GateDrain Source S IGS S ID BSIM4 LF Drain Current Noise Based on N- µ Model 3 noise parameters : NOIA NOIB NOIC NOIA = N t (E F ) in units of J -1 m -3 S IGD LF Gate-Drain noise model Correlation

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MOS – AK Montreux 18/09/06 22Outline Introduction Introduction Gate current low-frequency noise model and characterization Gate current low-frequency noise model and characterization Drain and gate current LFN Comparison Drain and gate current LFN Comparison Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Conclusion Conclusion

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MOS – AK Montreux 18/09/06 23 p-MOSFET Gate Leakage Current N P+ V D =-1V I GC I GDO V GS Saturation Range V DS = -1 V N P+ V D =-25 mV I GC I GDO V GS Low drain bias V DS = -25 mV

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MOS – AK Montreux 18/09/06 24 Gate to Channel Current Noise Characterization at low drain bias N P+ V D =-25 mV I GC V GS P+ V DS = -25 mV Gate to Channel leakage S VFB Extraction A single value of S VFB x WL allows to simulate the gate current noise of studied devices:

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MOS – AK Montreux 18/09/06 25 Gate to Channel Current Noise Characterization in Saturation Range N P+P+ P+ V D =-1V I GC V GS V DS = -1 V Gate to Channel leakage Same S VFB x WL Value for Saturation Range

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MOS – AK Montreux 18/09/06 26 Gate to Drain Overlap Current Noise Characterization (1/2) N P+ V DS I GC V GS =0 W/L = 10 µm / 10 µm W/L = 10 µm / 1 µm

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MOS – AK Montreux 18/09/06 27 Gate to Drain Overlap Current Noise Characterization (2/2) Extraction of S VFB for different Widths and L =10 µm The same Normalized S VFB is used to model the gate overlap current LF noise N P+ V DS I GC V GS =0

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MOS – AK Montreux 18/09/06 28 Gate Current Noise (On/Off state) Circuit Design point of view W/L = 10 µm / 10 µm W/L = 10 µm / 1 µm V DS = -1 V 1/f gate noise is higher in the off-state than in the on-state for short channel devices

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MOS – AK Montreux 18/09/06 29Outline Introduction Introduction Gate current low-frequency noise model and characterization Gate current low-frequency noise model and characterization Drain and gate current LFN Comparison Drain and gate current LFN Comparison Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Contributions of Channel Gate and Overlap Gate Currents on 1/f Gate Current Noise Conclusion Conclusion

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MOS – AK Montreux 18/09/06 30 Conclusion The 1/f gate current noise model involves slow oxide traps The 1/f gate current noise model involves slow oxide traps Extraction of slow oxide trap densities by gate current noise measurements Extraction of slow oxide trap densities by gate current noise measurements Good agreement with slow oxide trap densities extracted from drain current noise Good agreement with slow oxide trap densities extracted from drain current noise The same Flat Band voltage fluctuations are involved in both gate and drain LF noiseThe same Flat Band voltage fluctuations are involved in both gate and drain LF noise For short channel devices, gate current LF noise can be higher in the off- state than in the on-state. For short channel devices, gate current LF noise can be higher in the off- state than in the on-state. Implantation in MOSFET compact model Implantation in MOSFET compact model Formulation with NOIA BSIM4 noise parameter and gate LF noise partitionFormulation with NOIA BSIM4 noise parameter and gate LF noise partition

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