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1 Electrical Engineering 2 Microelectronics 2 Dr. Peter Ewen (Room G08, SMC; email - pjse) Lecture 13.

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Presentation on theme: "1 Electrical Engineering 2 Microelectronics 2 Dr. Peter Ewen (Room G08, SMC; email - pjse) Lecture 13."— Presentation transcript:

1 1 Electrical Engineering 2 Microelectronics 2 Dr. Peter Ewen (Room G08, SMC; - pjse) Lecture 13

2 2 The Abrupt Junction NDNDNDND Dopant concentration N A or N D Diffusion Implantation p n Depth into wafer, x xjxjxjxj ABRUPT JUNCTION ABRUPT JUNCTION Abrupt junction model NANANANA Dopant concentration N A or N D Depth into wafer, x NDNDNDND LINEARLY-GRADEDJUNCTION xjxjxjxj p n

3 p-type n-type -ve +ve junction depletionregion E The charges in the depletion region are those on the carriers and on the charged impurity ions fixed in the lattice. Taking the sign of the charges into account: c = e(p – n + N D – N A ) c = e(p – n + N D – N A ) = (p – n + N D – N A ) = (p – n + N D – N A ) dE e dx dx For simplicity take n = 0 & p = 0 – the depletion approximation

4 p-type n-type Charge density, c -eN A Distance, x eN D l p x=0 l n 0 Depletionregion Fig junction Charge density variation through a pn junction

5 5 To find the Electric Field For the p-type side we have: Poissons equation on p-type side Since N A is constant (abrupt junction) Since E = 0 outside the depletion region, i.e. at x I p Similarly, for the n-type side:

6 6 To find the Potential For the p-type side we have: The electric field, E, is defined by: If we take the zero of potential to be at x = 0 then C' = 0.

7 p-type n-type Potential, V Distance, x VBVBVBVB VpVpVpVp VnVnVnVn Electric field, E Distance, x E max EpEpEpEp EnEnEnEn Charge density, c -eN A Distance, x eN D 000 l p x=0 l n E

8 8 MOS Transistor – Basic Structure Fig. 80 n+n+n+n+ n+n+n+n+ Channel SiO 2 Source Gate Drain +V g n-channeldevice Metal Oxide Semiconductor p-type substrate

9 9 LECTURE 13 LECTURE 13 Operation of the MOS transistor Operation of the MOS transistor – gate-controlled surface effects – gate-controlled surface effects MOS fabrication MOS fabrication – enhancement and depletion devices – enhancement and depletion devices MOS Pinch-off MOS Pinch-off

10 10 p-typesubstrate drain source gate SiO 2 metal n+n+n+n+ n+n+n+n+ Charge ve voltageve voltage on gate QGQGQGQG QAQAQAQA (A Accumulation) Q A = -Q G QGQGQGQG QDQDQDQD +ve voltage on gate Channel forms when the +ve voltage on the gate is greater than V T (threshold voltage) QCQCQCQC (D Depletion) Q D = -Q G (C Channel) QC +QC +QC +QC + n-channel device (enhancement) Gate-Controlled Surface effects Fig. 81 Inversion occurs Distance holes acceptor ions electrons

11 11 n-typesubstrate drain source gate SiO 2 p+p+p+p+ p+p+p+p+ Charge -ve voltage on gate with magnitudegreater than V T p-channel device Gate-Controlled Surface effects Fig. 82 QCQCQCQC QDQDQDQD QGQGQGQG metal Distance

12 12 1.MOS Threshold Voltage An n-channel polysilicon gate MOS transistor has the following features: oxide thicknesst ox = 0.1 m channel widthW = 18 m channel lengthL = 6 m substrate dopingN A = 5x10 22 m -3 oxide relative permittivity ox = 4 E F E V for substrate = eV E g = 1.1 eV for Si (a) Determine the gate capacitance, C g. (b) If the depth of the depletion region at V G = V T is 0.14 m, how much of V T goes to creating Q D ?

13 13 1. MOS threshold voltage (a) Determine the gate capacitance, C g. n+n+n+n+ SiO 2 Gate Source Drain n+n+n+n+ n+n+n+n+ SiO 2 Source Drain n+n+n+n+ n+n+n+n+ SiO 2 conductor (metal) insulator (oxide) conductor (silicon) Source Drain n+n+n+n+ W L t ox oxide thicknesst ox = 0.1 m channel widthW = 18 m channel lengthL = 6 m substrate dopingN A = 5x10 22 m -3 oxide relative permittivity ox = 4 E F E V for substrate = eV E g = 1.1 eV for Si

14 14 (b) If the depth of the depletion region at V G = V T is 0.14 m, how much of V T goes to creating Q D ? Gate VTVT SiO 2 +ve _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ionised acceptor atoms _ _ _ _ _ _ _ _ _ _ _ _ _ _ inversion layer of electrons depletion region p-type substrate Gate region of n-channel MOS oxide thicknesst ox = 0.1 m channel widthW = 18 m channel lengthL = 6 m substrate dopingN A = 5x10 22 m -3 oxide relative permittivity ox = 4 E F E V for substrate = eV E g = 1.1 eV for Si

15 15 The part of V T that goes into creating the depletion charge Q D is therefore Gate VTVT SiO 2 +ve _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ p-type substrate Gate region of n-channel MOS _ _ _ _ L W Depth depth of depletion region – 0.14 m oxide thicknesst ox = 0.1 m channel widthW = 18 m channel lengthL = 6 m substrate dopingN A = 5x10 22 m -3 oxide relative permittivity ox = 4 E F E V for substrate = eV E g = 1.1 eV for Si

16 16 C.B. V.B. ECEVECEV 1.1eV n-channel (c) If effective inversion occurs when the channel is as n-type as the wafer is p-type, determine an approximate value for V T. C.B. V.B. ECEFEVECEFEV 1.1eV 0.175eV p-type substrate C.B. V.B. ECEFEVECEFEV 1.1eV 0.175eV n-channel For effective inversion E F must be 0.175eV below E C in the n-type channel, i.e. the band diagram must move down by: (1.1 – )eV = 0.75eV. (1.1 – )eV = 0.75eV

17 17 What voltage must be applied to the gate to achieve this?

18 18 p-type substrate (wafer) N A ~ m -3 SiO 2 polycrystalline Si (polysilicon) donor diffusion self-alignedgate n+n+n+n+ n+n+n+n+ MOS Fabrication n-channel enhancement device Fig. 83 Al Al Polysilicon Gate Source Drain n + + indicates heavy doping

19 19 n+n+n+n+ n+n+n+n+ SiO 2 Source Gate contact made here Drain Gate Contact Fig. 84 n-channeldevice

20 20 p-type substrate (wafer) N A ~ m -3 SiO 2 n+n+n+n+ n+n+n+n+ MOS Fabrication n-channel depletion device Al Al Polysilicon Gate Source Drain Implanted channel

21 21 n-channel enhancement device n+n+n+n+ n+n+n+n+ AlAl Implanted channel n+n+n+n+ n+n+n+n+ AlAl Polysilicon Gate Source Drain n-channel depletion device Polysilicon Gate Source Drain V T V GS I DS V T V GS I DS 0 0 Same considerations apply to p-channel devices. Same considerations apply to p-channel devices.

22 22 n-channel enhancement device MOS Pinch-off Fig. 85 source gate drain +8V 0V 0V +7V p-type substrate inversion layer n+n+n+n+ n+n+n+n+ V T = 1 V SiO 2 V ox V T everywhere between source and drain. +7.5V V ox drops below V T at drain end – channel becomes interrupted or pinched off depletionregion -eE

23 23 n-channel enhancement device Condition for pinch-off Fig. 86 source gate drain +8V+8V+8V+8V 0V 0V +7V n+n+n+n+ n+n+n+n+ V T = 1 V SiO 2 7.5V V ox is smallest at the drain end of the gate, hence pinch-off first occurs when V GD = V T V GD V GS V DS V GS V DS V GD G S D Pinch-off first appears when: V DS = V GS – V T V GD = V T V GS – V DS = V T V GS – V DS = V T V DS = V GS – V T V DS = V GS – V T

24 24 n-channel device Condition for pinch-off – all devices drain n+n+n+n+ V GS V DS V GD G S D V GD = V GS – V DS n+n+n+n+ gate p-channel device V GD < V T V GD < V T h V GS – V DS < V T V DS > V GS – V T V DS > V GS – V T V T +ve drain n+n+n+n+ V GD n+n+n+n+ gate V T -ve The channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. V GD ) is less than V T The channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. V GD ) is greater than V T V GD > V T V GD > V T h V GS – V DS > V T V DS < V GS – V T V DS < V GS – V T

25 25 n-channel enhancement device Conditions for pinch-off – all devices The channel will be pinched-off if: n-channel depletion device V DS > V GS – V T V DS < V GS – V T p-channel enhancement device p-channel depletion device n-channel enhancement device n-channel depletion device p-channel enhancement device p-channel depletion device V DS +ve+ve-ve-ve V GS +ve +ve or -ve -ve -ve or +ve VTVTVTVT+ve-ve-ve+ve

26 26 IDIDIDID V DS V DS =V GS -V T V DS >V GS -V T Effect of pinch-off on the current through the device source gate drain n+n+n+n+ n+n+n+n+ source gate drain n+n+n+n+ n+n+n+n+

27 27 2. Pinch-off The terminal voltages for an n-channel enhancement MOS transistor with V T = 1V are given below. Is the channel pinched off? V G = 5V V D = 4.5V V D = 4.5V V S = 3V

28 28 V GS – V T = 1, hence V DS > V GS – V T and so the channel is pinched off. To see if the channel is pinched off we need to compareV DS with V GS – V T. Device is n-channel so if V DS > V GS – V T the channel is pinched off V DS < V GS – V T the channel is not pinched off source gate drain +5V+5V+5V+5V 3V 3V +7V n+n+n+n+ n+n+n+n+ V T = 1 V 4.5V V GS V DS V DS is the voltage on the drain with respect to the source: V DS = V D – V S = 4.5 – 3 = 1.5V V GS is the voltage on the gate with respect to the source: V GS = V G – V S = 5 – 3 = 2V

29 29Summary MOS OPERATION MOS OPERATION n-channel device: V G 0 – no conduction between source and drain V G 0 – no conduction between source and drain possible because one of the two pn junctions possible because one of the two pn junctions around source and drain is reverse biased. around source and drain is reverse biased. 0 < V G < V T – mobile holes repelled from surface below gate. (V T is the Threshold Voltage.) 0 < V G < V T – mobile holes repelled from surface below gate. (V T is the Threshold Voltage.) V G > V T – electrons attracted to surface below gate, surface inverted to become n-type, conduction between source and drain. V G > V T – electrons attracted to surface below gate, surface inverted to become n-type, conduction between source and drain. p-typesubstrate source gate SiO 2 metal n+n+n+n+ n+n+n+n+ n-channel device (enhancement)

30 30 MOS FABRICATION MOS FABRICATION n-channel device: Lightly-doped p-type wafer Lightly-doped p-type wafer Grow thin SiO 2 layer for gate insulation Grow thin SiO 2 layer for gate insulation Deposit polycrystalline silicon for gate electrode Deposit polycrystalline silicon for gate electrode Diffuse/implant n-type dopant for source and drain (n + ) Diffuse/implant n-type dopant for source and drain (n + ) Make metal contacts – (gate contact offset) Make metal contacts – (gate contact offset)

31 31 ENHANCEMENT AND DEPLETION MOSFETs ENHANCEMENT AND DEPLETION MOSFETs Enhancement device – no channel between source and drain for V GS = 0 Depletion device – channel deliberately created between source and drain during fabrication. Hence there are 4 MOSFET types: n-channel enhancement n-channel depletion p-channel enhancement p-channel depletion

32 32 MOS PINCH-OFF MOS PINCH-OFF Channel between source and drain becomes pinched off (i.e. interrupted) when: V DS V GS – V T V DS V GS – V T IDIDIDID V DS V DS =V GS -V T V DS >V GS -V T


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