2 The Abrupt Junction Diffusion Implantation Abrupt junction model NA Dopant concentration NA or NDDopant concentration NA or NDp np nxjxjNDNDDepth into wafer, xDepth into wafer, xABRUPT JUNCTIONLINEARLY-GRADEDJUNCTION
3 c = e(p – n + ND – NA) = (p – n + ND – NA) junction p-type n-type - -ve +veThe charges in the depletion region are those on the carriers and on the charged impurity ions fixed in the lattice.EdepletionregionTaking the sign of the charges into account:c = e(p – n + ND – NA)dE edx = (p – n + ND – NA)For simplicity take n = 0 & p = 0 – the depletion approximation
4 Depletionregion-+--+-+++---++-+-+-++-++++---+-+---+--++-++-p-typelp x= lnn-typejunctionCharge density variation through a pn junctiondensity, cChargeeNDDistance, x-eNAFig. 76.2
5 To find the Electric Field For the p-type side we have:Poisson’s equation onp-type sideSince NA is constant(abrupt junction)Since E = 0 outside the depletion region, i.e. at x IpSimilarly, for the n-type side:
6 To find the Potential The electric field, E, is defined by: For the p-type side we have:If we take the zero of potential to be at x = 0 then C' = 0.
12 MOS Threshold VoltageAn n-channel polysilicon gate MOS transistor has the following features:oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3oxide relative permittivity ox = 4EF − EV for substrate = eVEg = 1.1 eV for SiDetermine the gate capacitance, Cg.If the depth of the depletion region at VG = VT is0.14 m, how much of VT goes to creating QD?
13 Determine the gate capacitance, Cg. oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3oxide relative permittivity ox = 4EF − EV for substrate = eVEg = 1.1 eV for Si1. MOS threshold voltageDetermine the gate capacitance, Cg.LSiO2SiO2SiO2WGateconductor (metal)insulator (oxide)conductor (silicon)SourceSourceSourceDrainDrainDrainn+n+n+n+n+n+tox
14 (b) If the depth of the depletion region at VG = VT is 0.14 m, how much of VTgoes to creating QD?oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3oxide relative permittivity ox = 4EF − EV for substrate = eVEg = 1.1 eV for SiGate region of n-channel MOSVT+veGateSiO2_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _inversion layer of electrons__depletion regionionised acceptor atomsp-type substrate
15 Gate region of n-channel MOS The part of VT that goes into creating the depletion charge QDis thereforedepth of depletion region – 0.14 moxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3oxide relative permittivity ox = 4EF − EV for substrate = eVEg = 1.1 eV for SiGate region of n-channel MOSGateVT+veSiO2_Depth_____WLp-type substrate
16 (c) If effective inversion occurs when the channel is as n-type as the wafer is p-type, determine an approximate value for VT.For effective inversion EF must be 0.175eV below EC in the n-type channel, i.e. the band diagram must move down by:(1.1 – 20.175)eV = 0.75eV.p-type substrateC.B.V.B.ECEFEV1.1eV0.175eVn-channelC.B.V.B.ECEV1.1eVn-channelC.B.ECEFEV(1.1 – 20.175)eV = 0.75eV1.1eV0.175eVV.B.
17 What voltage must be applied to the gate to achieve this?
21 Same considerations apply to p-channel devices. n-channel enhancement devicen-channel depletion devicePolysilicon GatePolysilicon GateSource DrainSource DrainAlAlAlAln+n+n+n+Implanted channelIDSIDSVT VGSVT VGSSame considerations apply to p-channel devices.
22 Vox ≥ VT everywhere between source and drain. MOS Pinch-offFig. 85n-channel enhancement device+8V+7.5V+7V0VVT = 1 VgatesourcedrainSiO2n+-eE→n+inversion layerdepletionregionp-type substrateVox ≥ VT everywhere between source and drain.Vox drops below VT at drain end – channel becomesinterrupted or “pinched off”
23 VGD = VT VGS – VDS = VT VDS = VGS – VT Condition for pinch-offFig. 86n-channel enhancement device+8Vgate7.5V+7V0VVT = 1 VVGSVGDsourcedrainSiO2n+n+VDSVox is smallest at the drain end of the gate, hence pinch-off first occurs when VGD = VTGVGDVGD = VT VGS – VDS = VT VDS = VGS – VTDVGSVDSSPinch-off first appears when: VDS = VGS – VT
24 Condition for pinch-off – all devices n-channel devicep-channel deviceThe channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. VGD) is less than VTThe channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. VGD) is greater than VTgategatedraindrainVGDVGDVT +veVT -ven+n+n+n+VGD = VGS – VDSGVGD > VTVGS – VDS > VT VDS < VGS – VTVGD < VTVGS – VDS < VT VDS > VGS – VTDVGSVDSS
25 Conditions for pinch-off – all devices The channel will be pinched-off if:n-channel enhancement deviceVDS > VGS – VTn-channel depletion devicep-channel enhancement deviceVDS < VGS – VTp-channel depletion devicen-channel enhancement devicen-channel depletion devicep-channel enhancement devicep-channel depletion deviceVDS+ve-veVGS+ve or -ve-ve or +veVT
26 sourcegatedrainn+sourcegatedrainn+IDVDS>VGS-VTVDS=VGS-VTVDSEffect of pinch-off on the current through the device
27 2. Pinch-offThe terminal voltages for an n-channel enhancement MOS transistor with VT = 1V are given below. Is the channel pinched off?VG = 5VVD = 4.5VVS = 3V
28 To see if the channel is pinched off we need to compareVDS with VGS – VT .Device is n-channel so ifVDS > VGS – VT the channel is pinched offVDS < VGS – VT the channel is not pinched offVDS is the voltage on the drain with respect to the source:VDS = VD – VS = 4.5 – 3 = 1.5VVGS is the voltage on the gate with respect to the source:VGS = VG – VS = 5 – 3 = 2VVGS – VT = 1, hence VDS > VGS – VT and so the channel is pinched off.+5V4.5V+7V3VVT = 1 VVGSgatesourcedrainn+n+VDS
29 Summary MOS OPERATION n-channel device: SiO2n+metaln-channel device(enhancement)gatep-typesubstrateMOS OPERATIONn-channel device:VG ≤ 0 – no conduction between source and drainpossible because one of the two pn junctionsaround source and drain is reverse biased.0 < VG < VT – mobile holes repelled from surface below gate. (VT is the Threshold Voltage.)VG > VT – electrons attracted to surface below gate, surface inverted to become n-type, conduction between source and drain.sourcen+
30 MOS FABRICATIONn-channel device:Lightly-doped p-type waferGrow thin SiO2 layer for gate insulationDeposit polycrystalline silicon for gate electrodeDiffuse/implant n-type dopant for source and drain (n+)Make metal contacts – (gate contact offset)
31 ENHANCEMENT AND DEPLETION MOSFET’s Enhancement device – no channel between source and drain for VGS = 0Depletion device – channel deliberately created between source and drain during fabrication.Hence there are 4 MOSFET types:n-channel enhancementn-channel depletionp-channel enhancementp-channel depletion
32 MOS PINCH-OFFChannel between source and drain becomes pinched off (i.e. interrupted) when:VDS ≥ VGS – VTIDVDSVDS=VGS-VTVDS>VGS-VT