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Background for Leakage Current Sept. 18, 2006 March 4, 2008.

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Presentation on theme: "Background for Leakage Current Sept. 18, 2006 March 4, 2008."— Presentation transcript:

1 Background for Leakage Current Sept. 18, 2006 March 4, 2008

2 Power Challenge Active power density increasing with device scaling and increased frequency Leakage power density increasing due to lower V t and gate leakage Stressing packaging, cooling, battery life, etc. Complicates IDDq testing as well Thinning gate oxides increase gate tunneling leakage Source from Bergamaschi

3 Problem Statement Power Analysis on CMOS Inverter

4 Problem Statement Dynamic Power Average Short Circuit Current Sub-threshold Leakage Current

5 Problem Statement Domination of Leakage Current Feature Size Core Voltage V TH (Threshold) Performance(AP) TR Leakage Stand-by Mode Low Power > 0.25um 5.0/3.3/2.5V > +/- 0.6V < 200MHz Negligible PLL-off(Clock-off) Focus on Operating Power 0.18/0.13/0.09um … 1.8/1.2/1.0V … +/- 0.5, 0.4, 0.3V … 300/400/533MHz, 1GHz Exponential growing(SD/Gate) V/MTMOS, High V TH /High VDD Focus on Operating/Stand-by

6 Active and Leakage Power with CMOS Scaling As CMOS scales down the following stand-by leakage current rises rapidly. –Source to drain leakage (diffusion+tunneling) as Lg scales down –Gate leakage current (tunneling) as Tox scales down –Body to drain leakage current (tunneling) as channel doping scales up

7 Two cases of Leakage Mechanism Vg=0V Turn off Vd=Vdd Turn on Vg=Vdd Vd=0V Sub-threshold Leakage Source to drain tunneling Drain to Body tunneling (BTB) Gate oxide tunneling

8 Gate Leakage Current Reduction with High-K Gate Dielectric Current Density (A/cm 2 ) Tox (A) Gate leakage Drain leakage High-K gate dielectric

9 Voltage Scaling for Low Power Low Power Low VDD Low Speed Speed Up Low V th P  VDD 2 I ds  (VDD - V th ) 1~2 High Leakage I leakage  e -C x Vth Leakage Suppression

10 Low-Leakage Solution – Technology Dynamic power[W] Leakage power[W] V TH : 0.5VV TH : 0.25V High speed Low speed VDD control V TH control High speed MTCMOS VDD: 1.5V VDD: 1.0V VDD control V TH control 100n 11 10  100  100p 1p 10p 100n 1n 10n

11 VTCMOS & MTCMOS Multi-Threshold CMOS Variable-Threshold CMOS Schematic Diagram principle On-off control of internal VDD or VSS Special F/Fs, Two Vth’s On-off control of internal VDD or VSS Special F/Fs, Two Vth’s Threshold control with bulk-bias Triple well is desirable Threshold control with bulk-bias Triple well is desirable Low leakage in stand-by mode. Conventional design Env. Low leakage in stand-by mode. Conventional design Env. Merit Low leakage in stand-by mode. Conventional design Env. Low leakage in stand-by mode. Conventional design Env. Demerit Large serial MOSFET ground bounce noise Ultra-low voltage region?(1V) Large serial MOSFET ground bounce noise Ultra-low voltage region?(1V) Scalability? (junction leakage) TR reliability under 0.1  m Latch-up immunity, Vth controllability, Substrate noise, Gate oxide reliability Gate leakage current Scalability? (junction leakage) TR reliability under 0.1  m Latch-up immunity, Vth controllability, Substrate noise, Gate oxide reliability Gate leakage current Low-Vth VDD GND Hi-VthSleep LowVt VDD GND Vt Control circuit Vnb= 0 or V- Vpb = VDD or V+ N-well P-well

12 MTCMOS : Reduce Stand-by Power with High Speed With High V TH switch, much lower leakage current flows between Vdd and Vss High V TH MOSFET should have much lower ( >10X) leakage current compared to normal V TH MOSFET Vdd Vss 0 0 Vdd Vss Without High V TH switch With High V TH switch (MTCMOS) High V TH switch Normal or Low V TH MOSFET Virtual Ground

13 Multi-Threshold CMOS (MTCMOS) Mobile Applications –Mostly in the idle state –Sub-threshold leakage Current Power Gating –Low V TH Transistors for High Performance Logic Gates –High V TH Transistors for Low Leakage Current Gates ActiveSleepActive Sleep Control (SC) Time Operating Mode Current Cutoff-Switch (High V th ) SC VDD VSS VGND Low V th MOS High V th MOS Logic Component (Low V th )

14 CCS Sizing The effect of CCS (current-controlled switch) size –As the size decreases, logic performance also decreases. –As the size increases, leakage current and chip area also increase. –Proper sizing is very important. –CCS size should be decided within 2% performance degradation. Vop = VDD -  V  V must be sized within 2% performance degradation. VDD GND Low Vt HighVt Switch Control

15 Leakage Current : Limiting Factor in VDSM Technology C.M.Kyung

16 ITRS roadmap Scaling down allows the same performance with reduced voltage, leading to low power. From 0.18 micron down, building a transistor with a good active current(I on ) and a low leakage current (I off ) is difficult. –high-speed TR’s ; low channel doping –low-leakage TR’s ; high channel doping Now three groups of TR’s; –High Performance (HP) ; high active current ; Thin T ox –Low Operating Power (LOP) ; low active current ; High T ox –Low Standby Power (LSTP) ; low static current ; High T ox

17 Device characteristics for HP, LOP, and LSTP Technologies

18 Reference : Low-Power CMOS Circuits technology, logic design and CAD tools By Christian Piguet CRC Taylor and Francis 2005

19 Bulk CMOS vs. SOI Buried oxide layer below active silicon layer -> electrical isolation of TR’s –Lower parasitic cap. PD(Partially Depleted) –Floating body effect increases speed Low threshold in dynamic mode or FD(Fully Depl) –Ideal subthresold swing of 60 mV/decade

20 Reducing Subthreshold current in Bulk CMOS VTCMOS (Variable Threshold) –Tune substrate bias to adjust V th –Requires efficient DC-DC converter –For a given technology, there an optimum in V R, as decreasing subthreshold leakage is accompanied by an increase in drain junction leakage When both High Vt and Low Vt TR’s are available, –MTCMOS (Multi-Threshold) ; Introduce high Vt power switch to limit leakage in stby mode –Use low Vt for critical path –This can be coupled with multiple VDD’s Other tricks –Set up the logical internal states where the total leakage is minimal.

21 Five types of off-currents Tunneling through gate oxide –Fowler-Nordheim tunneling -> direct tunneling Subthreshold current Gate-induced drain leakage (GIDL) –Thermal emission –Trap-assisted tunneling –BTBT Reverse-biased pn junction current –-> band-to-band tunneling (BTBT) current Bulk punch-through

22 Gate-induced drain leakage (GIDL) –Thermal emission –Trap-assisted tunneling –BTBT Fig 3.12

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24 Leakage current due to QM Tunneling substrate and drain ; band-to-band tunneling ; –increases with E-field and dopant concentration due to scaling source and drain ; –Surface punchthru due to DIBL –Punch-through at bulk gate oxide ; –SiO2 has been used as it has so low trap and fixed charge density at the interface –Gate current is an exponential function of Tox and Vox –Hole tunneling is 10% of that of electron due to higher barrier height and heavier effective mass

25 Gate Leakage Current Reduction with High-K Gate Dielectric As Tox scales gate leakage current increases exponentially due to exponential increase of tunneling probability with reduction of physical tunneling distance. Physically thicker gate dielectric allows lower leakage current but lower oxide capacitance reducing on-current Using high k (dielectric constant) material, both thicker physical thickness and higher oxide capacitance can be achieved. Applying high-k gate dielectric, several orders of magnitude lower gate leakage current can be achieved with similar oxide capacitance

26 Approach 1 to reduce gate leakage ; High K materials To suppress gate tunneling current, use materials with –High K -> increases thickness (t) –Higher barrier height (h) Using high K –Increases short-channel effects due to thicker gate dielectric (This sets an upper limit on K, lower limit coming from I tunnel) –Mobility degradation due to poor interface quality

27 Approach 2 to reduce gate leakage ; stop scaling the thickness of gate oxide Thicker gate oxide yields less control of gate on channel conduction, i.e., higher short-channel effects and DIBL effects.

28 Approach 3 to reduce gate leakage Multiple gates allows better control of channel by gate, and lets scaling continue without excessive short-channel effects –Double gate –FinFET –Triple gate –Quadruple or gate all-around

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