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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Overview

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Combinational vs. Sequential Logic

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Static CMOS

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic PMOS Transistors in Series/Parallel Connection

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Complementary CMOS Logic Style Construction (cont.)

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Example Gate: NAND

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Example Gate: NOR

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Example Gate: COMPLEX CMOS GATE

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic 4-input NAND Gate In1In2In3In4 Vdd GND Out

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Standard Cell Layout Methodology

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Two Versions of (a+b).c

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Logic Graph

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Consistent Euler Path

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Example: x = ab+cd

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Properties of Complementary CMOS Gates

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Properties of Complementary CMOS Gates

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Transistor Sizing

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Propagation Delay Analysis - The Switch Model

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic What is the Value of R on ?

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Numerical Examples of Resistances for 1.2 m CMOS

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Analysis of Propagation Delay

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Design for Worst Case

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Influence of Fan-In and Fan-Out on Delay

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic t p as a function of Fan-In

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Fast Complex Gate - Design Techniques

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Fast Complex Gate - Design Techniques (2)

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Fast Complex Gate - Design Techniques (3)

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Fast Complex Gate - Design Techniques (4)

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic Example: Full Adder

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Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic A Revised Adder Circuit

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