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**ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison**

Dept. of Electrical & Computer Engineering

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Ratioed logic

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Ratioed Logic

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Ratioed Logic

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Active Loads

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Pseudo-NMOS

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Revist: PLA Schematic

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Pseudo-NMOS VTC

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Improved Loads

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**Differential Cascode Voltage Switch Logic (DCVSL)**

Improved Loads (2) V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Differential Cascode Voltage Switch Logic (DCVSL)

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DCVSL Example

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**DCVSL Transient Response**

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Dynamic CMOS DESIGN

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Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

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**Dynamic Gate Out Clk A B C Clk Out CL In1 In2 PDN In3 Clk**

Mp Me Clk Mp Out CL In1 In2 PDN In3 Clk Me Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

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**Dynamic Gate Out Clk A B C off Clk on 1 Out CL ((AB)+C) In1 In2 PDN**

Mp Me off Clk Mp on 1 Out CL ((AB)+C) In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

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Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

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**Properties of Dynamic Gates**

Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL

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**Properties of Dynamic Gates**

Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock

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**Issues in Dynamic Design 1:**

Charge Leakage CLK Clk Mp Out CL A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

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**Solution to Charge Leakage**

Keeper Clk Mp Mkp CL A Out B Clk Me Same approach as level restorer for pass-transistor logic

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**Issues in Dynamic Design 2:**

Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out CL A CA B=0 CB Clk Me

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**Charge Sharing Example**

Clk Out CL=50fF A A Ca=15fF B Cb=15fF B B !B Cc=15fF Cd=10fF C C Clk

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Charge Sharing V DD Clk M p Out C L A M a X C a B = M b C b Clk M e

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**Solution to Charge Redistribution**

Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

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**Issues in Dynamic Design 3:**

Backgate Coupling Clk Mp Out1 =1 Out2 =0 CL1 CL2 In A=0 B=0 Clk Me Dynamic NAND Static NAND

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**Backgate Coupling Effect**

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**Issues in Dynamic Design 4**

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out CL A B Clk Me

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**Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk In4**

Voltage In4 Out Clk Time, ns Clock feedthrough

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**Cascading Dynamic Gates**

V Clk Clk Clk Mp Mp Out2 Out1 In In Out1 VTn Clk Clk Me Me Out2 V t Only 0 1 transitions allowed at inputs!

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**Domino Logic Only non-inverting logic can be implemented**

Clk Mp Mkp Clk Mp Out1 Out2 1 1 1 0 0 0 0 1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort

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Why Domino? Like falling dominos!

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**Designing with Domino Logic**

V DD V DD V DD Clk M Clk M p p M Out1 r Out2 In 1 In PDN In PDN 2 4 In 3 Can be eliminated! Clk M e Clk M e Inputs = 0 during precharge

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**Differential (Dual Rail) Domino**

off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB A !A !B B Clk Me Solves the problem of non-inverting logic

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**NP-CMOS Clk Clk Out1 In4 PUN In1 In5 In2 PDN In3 Out2 (to PDN) Clk Clk**

Me Clk Mp Out1 1 1 1 0 In4 PUN In1 In5 In2 PDN 0 0 0 1 In3 Out2 (to PDN) Clk Mp Clk Me Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

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