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ECE 555 Digital Circuits & Components ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1.

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Presentation on theme: "ECE 555 Digital Circuits & Components ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1."— Presentation transcript:

1 ECE 555 Digital Circuits & Components ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1

2 RATIOED LOGIC 2

3 ECE 555 Digital Circuits & Components Ratioed Logic 3

4 ECE 555 Digital Circuits & Components Ratioed Logic 4

5 ECE 555 Digital Circuits & Components Active Loads 5

6 ECE 555 Digital Circuits & Components Pseudo-NMOS 6

7 Revist: PLA Schematic 7

8 ECE 555 Digital Circuits & Components Pseudo-NMOS VTC 8

9 ECE 555 Digital Circuits & Components Improved Loads 9

10 ECE 555 Digital Circuits & Components Improved Loads (2) 10 V DD V SS PDN1 Out V DD V SS PDN2 Out A A B B M1M2 Differential Cascode Voltage Switch Logic (DCVSL)

11 ECE 555 Digital Circuits & Components DCVSL Example 11

12 ECE 555 Digital Circuits & Components DCVSL Transient Response 12

13 DYNAMIC CMOS DESIGN 13

14 ECE 555 Digital Circuits & Components Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors 14

15 ECE 555 Digital Circuits & Components Dynamic Gate 15 In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

16 ECE 555 Digital Circuits & Components Dynamic Gate 16 In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)

17 ECE 555 Digital Circuits & Components Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L 17

18 ECE 555 Digital Circuits & Components Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) no I sc, so all the current provided by PDN goes into discharging C L 18

19 ECE 555 Digital Circuits & Components Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock 19

20 ECE 555 Digital Circuits & Components Issues in Dynamic Design 1: Charge Leakage 20 CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is subthreshold current

21 ECE 555 Digital Circuits & Components Solution to Charge Leakage 21 CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

22 ECE 555 Digital Circuits & Components Issues in Dynamic Design 2: Charge Sharing 22 CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

23 ECE 555 Digital Circuits & Components Charge Sharing Example 23 C L =50fF Clk AA B B B!B CC Out C a =15fFC c =15fFC b =15fFC d =10fF

24 ECE 555 Digital Circuits & Components Charge Sharing 24 B 0 Clk X C L C a C b A Out M p M a V DD M b Clk M e

25 ECE 555 Digital Circuits & Components Solution to Charge Redistribution 25 Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

26 ECE 555 Digital Circuits & Components Issues in Dynamic Design 3: Backgate Coupling 26 C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0

27 ECE 555 Digital Circuits & Components Backgate Coupling Effect 27

28 ECE 555 Digital Circuits & Components Issues in Dynamic Design 4 28 CLCL Clk B A Out MpMp MeMe Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

29 ECE 555 Digital Circuits & Components Clock Feedthrough 29 Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feedthrough

30 ECE 555 Digital Circuits & Components Cascading Dynamic Gates 30 Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 V V Tn Only 0 1 transitions allowed at inputs!

31 ECE 555 Digital Circuits & Components Domino Logic 31 In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort

32 ECE 555 Digital Circuits & Components Why Domino? 32 Like falling dominos!

33 ECE 555 Digital Circuits & Components Designing with Domino Logic 33 M p M e V DD PDN Clk In Out1 Clk M p M e V DD PDN Clk In 4 Clk Out2 M r V DD Inputs = 0 during precharge Can be eliminated!

34 ECE 555 Digital Circuits & Components Differential (Dual Rail) Domino 34 A B MeMe MpMp Clk Out = AB !A!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off

35 ECE 555 Digital Circuits & Components NP-CMOS 35 In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN


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