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Pass Transistor Logic

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Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies

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Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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nMOS Pass Transistor – Logic ‘1’ Transfer

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nMOS Pass Transistor – Logic ‘0’ Transfer

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PASS TRANSISTORS IN SERIES

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PASS TRANSISTOR LOGIC CIRCUITS nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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TRANSMISSION GATES NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

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TRANSMISSION GATE

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PROBLEMS WITH TRANSMISSION GATES No isolation between the input and output. Output progressively deteriorates as it passes through various stages. However designs get simplified.

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TRANSMISSION GATE - LAYOUT

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PASS TRANSISTOR LOGIC CIRCUITS nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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Multiplexor

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Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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XOR gate

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PASS TRANSISTOR LOGIC CIRCUITS nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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D – Latch

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TIMING ISSUES

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D LATCH

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D - LATCH

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D LATCH – ALTERNATE CIRCUIT TOPOLOGY

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PASS TRANSISTOR LOGIC CIRCUITS nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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Static Flip Flop 0 1 D 1 0 Q Clk Transparent when Clk=0Transparent when Clk=1 At Clk= 0 1, Q = D. Else Q is held.

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D Flip Flop – Circuit Diagram

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D Flip Flop - Operation

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D Flip Flop - Waveforms

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Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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Handling Clock Skew Clk-in Clk Clk'

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Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications Mux XOR D Latch D Flip Flop Clock Skew management Pass Transistor Logic Families

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Pass Transistor Logic Families Complementary Pass Transistor Logic Family Dual Pass Transistor Logic Family Swing Restored Pass Transistor Logic Family

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Problems Design 4 to 1 multiplexor using transmission-gates. Implement an XOR gate using minimum number of transistors. Implement a full adder using transmission gates.

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Solution - 1 C'0C'0 C0C0 C1C1 C'1C'1 Y A0 A1 A2 A3

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Solution - 2 C'0C'0 C0C0 C'1C'1 A0 A1 A2 A3 C1C1 Y

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XOR Gate AB ABAB

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