Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Presentation on theme: "Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures."— Presentation transcript:

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Combinational logic expressions n Combinational logic: function value is a combination of function arguments. n A logic gate implements a particular logic function. n Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Gate design Why designing gates for logic functions is non-trivial: –may not have logic gates in the library for all logic expressions; –a logic expression may map into gates that consume a lot of area, delay, or power.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Boolean algebra terminology n Function: f = ab + ab n a is a variable; a and a are literals. n ab is a term. n A function is irredundant if no literal can be removed without changing its truth value.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Completeness n A set of functions f1, f2,... is complete iff every Boolean function can be generated by a combination of the functions. n NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. n NOT = NAND with shorted inputs. n AND = NAND followed by a NOT. n OR = Two inverters followed by a NAND. n Transmission gates are not complete. n If your set of logic gates is not complete, you cant design arbitrary logic.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Static complementary gates n Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. n Static: do not rely on stored charge. n Simple, effective, reliable; hence ubiquitous.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Static complementary gate structure Pullup and pulldown networks: pullup network pulldown network V DD V SS out inputs

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Inverter a out +

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Inverter layout (tubs not shown) a out + transistors GND VDD aout tub ties

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR NAND gate + b a out

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR NAND layout + b a out b a VDD GND tub ties

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR NOR gate + b a out

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR NOR layout b a out a b VDD GND tub ties

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR AOI/OAI gates n AOI = and/or/invert; OAI = or/and/invert. n Implement larger functions. n Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents. n AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR AOI example out = [ab+c]: symbolpull-up circuit and or invert pull-down circuit

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Pullup/pulldown network design n Pullup and pulldown networks are duals. n To design a CMOS logic circuit for a combinational expression, first design a pull-down network for it, then compute the dual to get the pull-up network.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Dual network construction dummy a bc a b c

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Dual network construction The pull-up part of a CMOS implementation of f can be obtained by writing a sum-of-product expression for f and likewise the pull-down part can be obtained by writing a sum-of-product expression for f. Note: As we discussed in class, it is not always possible to use p-type transistors in the pull-up circuit and/or n- type transistors in the pull-down circuit unless we use inverter gates for negated inputs in certain cases. For example, (AB + CD) cannot be realized all with p-type transistors unless we use an inverter to generate A.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Dual network construction (AB + CD) GND v DD GND A C B D A B C D (AB + CD) (AB + CD) = (A +B)(C+D)

Similar presentations