 # Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring.

## Presentation on theme: "Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring."— Presentation transcript:

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 EECS 40 Spring 2003 Lecture 23 Computing Gate Delay 4/1/03 Prof. Andy Neureuther Discharging Capacitance through a MOS device? Equivalent resistance model for MOS CMOS Logic operation Path dependent delay Worst cae and Cascade

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Transient Gate Problem: Discharging and Charging Capacitance on the Output V OUT I OUT Output V IN-D V DD V IN-U p-type MOS Transistor (PMOS) n-type MOS Transistor (NMOS) V IN = V DD = 5V C OUT = 50 fF 5V => 0

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Output Propagation Delay High to Low V OUT (0) = 5V C OUT = 50 fF I OUT-SAT-D = 100  A V OUT (V) 035 I OUT (  A) 2020 60 100 V IN = 5V I OUT-SAT-D = 100  A When V IN goes High V OUT starts decreases with time Assume that the necessary voltage swing to cause the next downstream gate to begin to switch is V DD /2 or 2.5V. That is the propagation delay  HL for the output to go from high to low is the time to go from V DD = 5V to to V DD /2 =2.5V

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Output Propagation Delay High to Low (Cont.) When V OUT > V OUT-SAT-D the available current is I OUT-SAT-D V OUT (0) = 5V C OUT = 50 fF I OUT-SAT-D = 100  A V OUT (V) 035 I OUT (  A) 2020 60 100 V IN = 5V I OUT-SAT-D = 100  A The propagation delay is thus For this circuit when V OUT > V OUT-SAT-D the available current is constant at I OUT-SAT-D and the capacitor discharges.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Switched Equivalent Resistance Model The above model assumes the device is an ideal constant current source. 1) This is not true below V OUT-SAT-D and leads to in accuracies. 2) Combining ideal current sources in networks with series and parallel connections is problematic. Instead define an equivalent resistance for the device by setting 0.69R D C equal to the  t found above This gives Each device can now be replaced by this equivalent resistor. RDRD

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 ¾ V DD /I SAT Physical Interpretation V OUT (0) = 5V C OUT = 50 fF I OUT-SAT-D = 100  A V OUT (V) 035 I OUT (  A) 2020 60 100 V IN = 5V I OUT-SAT-D = 100  A ¾ V DD is the average value of V OUT Approximate the NMOS device curve by a straight line from (0,0) to (I OUT-SAT-D, ¾ V DD ). Interpret the straight line as a resistor with 1/(slope) = R = ¾ V DD /I SAT

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Switched Equivalent Resistance Values The resistor values depend on the properties of silicon, geometrical layout, design style and technology node. n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type. The resistance is inversely proportion to the gate width/length in the geometrical layout. Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size. The current per unit width of the gate increases nearly inversely with the linewidth. For convenience in EE 42 we assume R D = R U = 10 k 

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Inverter Propagation Delay  t = 0.69R D C OUT = 0.69(10k  )(50fF) = 345 ps Discharge (pull-down) Discharge (pull-up)  t = 0.69R U C OUT = 0.69(10k  )(50fF) = 345 ps V OUT V DD V IN = Vdd C OUT = 50fF V OUT V DD V IN = Vdd RDRD C OUT = 50fF

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 CMOS Logic Gate A B C A B C V DD V OUT NMOS conduct when input is high. PMOS only in pull-up NMOS and PMOS use the same set of input signals PMOS conduct when input is low NMOS only in pull-down NMOS conduct for A + (BC) PMOS do not conduct when A +(BC) Logic is Complementary and produces F = A + (BC)

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 CMOS Logic Gate: Example Inputs A B C A B C V DD V OUT NMOS do not conduct Logic is Complementary and produces F = 1 A = 0 PMOS all conduct Output is High = V DD B = 0 C = 0

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 CMOS Logic Gate: Example Inputs A B C A B C V DD V OUT NMOS B and C conduct; A open Logic is Complementary and produces F = 0 PMOS A conducts; B and C Open Output is Low = 0 A = 0 B = 1 C = 1

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Switched Equivalent Resistance Network A B C A B C V DD V OUT A B C A B C V DD V OUT RURU RURU RURU RDRD RDRD RDRD Switches close when input is high. Switches close when input is low.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Logic Gate Propagation Delay: Initial State The initial state depends on the old (previous) inputs. A B C A B C V DD V OUT RURU RURU RURU RDRD RDRD RDRD C OUT = 50 fF Example: A=0, B=0, C=0 for a long time. These inputs provided a path to V DD for a long time and the capacitor has precharged up to V DD = 5V.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Logic Gate Propagation Delay: Transient Example: At t=0, B and C switch from low to high (V DD ) and A remains low. A B C A B C V DD V OUT RURU RURU RURU RDRD RDRD RDRD C OUT = 50 fF C OUT discharges through the pull-down resistance of gates B and C in series.  t = 0.69(R DB +R DC )C OUT = 0.69(20k  )(50fF) = 690 ps The propagation delay is two times longer than that for the inverter! This breaks the path from V OUT to V DD And opens a path from V OUT to GND The equivalent resistance of the pull-down or pull- up network for the transient phase depends on the new present input state.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Logic Gate: Worst Case Scenarios What combination of previous and present logic inputs will make the Pull-Down the fastest? What combination of previous and present logic inputs will make the Pull-Down the slowest? What combination of previous and present logic inputs will make the Pull-Up the fastest? What combination of previous and present logic inputs will make the Pull-Up the slowest? Fastest overall? Slowest overall? A B C A B C V DD V OUT RURU RURU RURU RDRD RDRD RDRD C OUT = 50 fF

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring 2003 Logic Gate Cascade To avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks. The four independent input are A1, B1, A2 and C2. Fastest: A2 high discharges gate 2 without even waiting for the output of gate 1. Slowest: C2 high and A2 low makes gate 2 wait for Gate 1 output A2 B2 V DD A1 B1 A1 B1 V DD V OUT 1 B2 C2 A2 C2 V OUT 2 50 fF B2 = V OUT 1

Download ppt "Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring."

Similar presentations