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La logica combinatoria1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 6 18.3.2011 La logica combinatoria

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2 Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

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La logica combinatoria3 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

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La logica combinatoria4 Static Complementary CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … …

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La logica combinatoria5 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

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La logica combinatoria6 PMOS Transistors in Series/Parallel Connection

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La logica combinatoria7 Threshold Drops V DD V DD 0 PDN 0 V DD CLCL CLCL PUN V DD 0 V DD - V Tn CLCL V DD V DD |V Tp | CLCL S DS D V GS S SD D

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La logica combinatoria8 Complementary CMOS Logic Style

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La logica combinatoria9 Example Gate: NAND P

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La logica combinatoria10 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

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La logica combinatoria11 Constructing a Complex Gate

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La logica combinatoria12 Cell Design Standard Cells –General purpose logic –Can be synthesized –Same height, varying width Datapath Cells –For regular, structured designs (arithmetic) –Includes some wiring in the cell –Fixed height and width

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La logica combinatoria13 Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rails ~10 In Out V DD GND

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La logica combinatoria14 Standard Cells A Out V DD GND B 2-input NAND gate

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La logica combinatoria15 Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2

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La logica combinatoria16 Stick Diagrams C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph

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La logica combinatoria17 Two Versions of C (A + B) X CABABC X V DD GND V DD GND

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La logica combinatoria18 Consistent Euler Path j V DD X X i GND AB C ABC

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La logica combinatoria19 OAI22 Logic Graph C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

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La logica combinatoria20 Example: x = ab+cd

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La logica combinatoria21 Properties of Complementary CMOS Gates Snapshot High noise margins: V OH andV OL are atV DD andGND, respectively. No static power consumption: There never exists a direct path betweenV DD and V SS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions)

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La logica combinatoria22 CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors

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La logica combinatoria23 Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 INV NOR2

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La logica combinatoria24 Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition –both inputs go low delay is 0.69 R p /2 C L –one input goes low delay is 0.69 R p C L High to low transition –both inputs go high delay is 0.69 2R n C L CLCL B RnRn A RpRp B RpRp A RnRn C int

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La logica combinatoria25 Delay Dependence on Input Patterns A=B=1 0 A=1, B=1 0 A=1 0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0 1 67 A=1, B=0 1 64 A= 0 1, B=1 61 A=B=1 0 45 A=1, B=1 0 80 A= 1 0, B=1 81 NMOS = 0.5 m/0.25 m PMOS = 0.75 m/0.25 m C L = 100 fF

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La logica combinatoria26 Transistor Sizing CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL 2222 22 1 1 4444

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La logica combinatoria27 Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C 1 2 22 4 4 8 8 6 3 6 6

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La logica combinatoria28 Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

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La logica combinatoria29 t p as a Function of Fan-In t pL H t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided. t pH L quadratic linear tptp

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La logica combinatoria30 t p as a Function of Fan-Out t p NOR2 t p (psec) eff. fan-out All gates have the same drive current. t p NAND2 t p INV Slope is a function of “driving strength”

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La logica combinatoria31 t p as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO

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La logica combinatoria32 Fast Complex Gates: Design Technique 1 Transistor sizing –as long as fan-out capacitance dominates Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the mos closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks

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La logica combinatoria33 Fast Complex Gates: Design Technique 2 Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 1 1 0101 charged discharged

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La logica combinatoria34 Fast Complex Gates: Design Technique 3 Isolating fan-in from fan-out using buffer insertion CLCL CLCL

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La logica combinatoria35 Fast Complex Gates: Design Technique 4 Reducing the voltage swing –linear reduction in delay –also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.69 (3/4 (C L V swing )/ I DSATn )

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La logica combinatoria36 Sizing Logic Paths for Speed Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain – can we generalize it for any type of logic?

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La logica combinatoria37 Buffer Example For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N (in units of inv )

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La logica combinatoria38 Logical Effort p – intrinsic delay (3kR unit C unit ) - gate parameter f(W) g – logical effort (kR unit C unit ) – gate parameter f(W) f – effective fanout Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by inv (everything is measured in unit delays inv ) Assume = 1.

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La logica combinatoria39 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

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La logica combinatoria40 Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity

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La logica combinatoria41 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3

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La logica combinatoria42 Logical Effort of Gates

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La logica combinatoria43 Add Branching Effort Branching effort:

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La logica combinatoria44 Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 …g N Branching effort: B = b 1 b 2 …b N Path effort: H = GFB Path delay D = d i = p i + h i

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La logica combinatoria45 Optimum Effort per Stage When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

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La logica combinatoria46 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

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La logica combinatoria47 Logical Effort From Sutherland, Sproull

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La logica combinatoria48 Method of Logical Effort Compute the path effort: F = GBH Find the best number of stages N ~ log 4 F Compute the stage effort f = F 1/N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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La logica combinatoria49 Summary Sutherland, Sproull Harris

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La logica combinatoria50 Power If well designed, the dynamic power prevails P=α 0 1 C L V DD 2 α 0 1 is activity factor = 0.5 for the inverter

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La logica combinatoria51 Ratioed Logic

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La logica combinatoria52 Ratioed Logic

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La logica combinatoria53 Active Loads

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La logica combinatoria54 Pseudo-NMOS

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La logica combinatoria55

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La logica combinatoria56 Pass-Transistor Logic

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La logica combinatoria57 Pass-Transistor Logic

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La logica combinatoria58 Example: AND Gate

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La logica combinatoria59

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La logica combinatoria61

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La logica combinatoria62 Resistance of Transmission Gate

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La logica combinatoria63

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La logica combinatoria64

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La logica combinatoria65 Delay Optimization

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La logica combinatoria66 Dynamic Logic

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La logica combinatoria67 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. –fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. –requires on n + 2 (n+1 N-type + 1 P-type) transistors

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La logica combinatoria68 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

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La logica combinatoria69 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)

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La logica combinatoria70 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

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La logica combinatoria71 Properties of Dynamic Gates Logic function is implemented by the PDN only –number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds –reduced load capacitance due to lower input capacitance (C in ) –reduced load capacitance due to smaller output loading (Cout) –no I sc, so all the current provided by PDN goes into discharging C L

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La logica combinatoria72 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS –no static current path ever exists between V DD and GND (including P sc ) –no glitching –higher transition probabilities –extra load on Clk PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn –low noise margin (NM L ) Needs a precharge/evaluate clock

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La logica combinatoria73 Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

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La logica combinatoria74 Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

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La logica combinatoria75 Charge Sharing B 0 Clk X C L C a C b A Out M p M a V DD M b Clk M e

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La logica combinatoria76 Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

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La logica combinatoria77 Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0

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La logica combinatoria78 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)

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La logica combinatoria79 Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t Clk In Out1 Out2 VV V Tn Only 0 1 transitions allowed at inputs!

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La logica combinatoria80 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1 1 1 0 0 0 0 1

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La logica combinatoria81 Why Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

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La logica combinatoria82 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed –static inverter can be skewed, only L-H transition –Input capacitance reduced – smaller logical effort

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La logica combinatoria83

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La logica combinatoria84 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

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La logica combinatoria85 Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off

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La logica combinatoria86 np-CMOS In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1 1 1 0 0 0 0 1 Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

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