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Published byEmmalee Boutwell Modified over 2 years ago

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**Progettazione di circuiti e sistemi VLSI La logica combinatoria**

Anno Accademico Lezione 6 La logica combinatoria La logica combinatoria

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**Combinational vs. Sequential Logic**

Output = f ( In ) Output = f ( In, Previous In ) La logica combinatoria

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**La logica combinatoria**

Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. La logica combinatoria

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**Static Complementary CMOS**

VDD F(In1,In2,…InN) In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … La logica combinatoria

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**NMOS Transistors in Series/Parallel Connection**

Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high La logica combinatoria

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**PMOS Transistors in Series/Parallel Connection**

La logica combinatoria

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**La logica combinatoria**

Threshold Drops VDD VDD 0 PDN 0 VDD CL PUN 0 VDD - VTn VDD |VTp| S D VGS La logica combinatoria

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**Complementary CMOS Logic Style**

La logica combinatoria

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**La logica combinatoria**

Example Gate: NAND P La logica combinatoria

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**La logica combinatoria**

Complex CMOS Gate B C A D OUT = D + A • (B + C) A D B C La logica combinatoria

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**Constructing a Complex Gate**

La logica combinatoria

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**La logica combinatoria**

Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width La logica combinatoria

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**La logica combinatoria**

Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rails ~10 In Out V DD GND La logica combinatoria

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**La logica combinatoria**

Standard Cells A Out V DD GND B 2-input NAND gate La logica combinatoria

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**La logica combinatoria**

Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A B NAND2 La logica combinatoria

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**La logica combinatoria**

Stick Diagrams C A B X = C • (A + B) i j VDD X GND PUN PDN Logic Graph La logica combinatoria

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**Two Versions of C • (A + B)**

X C A B VDD GND La logica combinatoria

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**La logica combinatoria**

Consistent Euler Path j VDD X i GND A B C La logica combinatoria

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**La logica combinatoria**

OAI22 Logic Graph C A B X = (A+B)•(C+D) D VDD X GND PUN PDN La logica combinatoria

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**La logica combinatoria**

Example: x = ab+cd La logica combinatoria

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**Properties of Complementary CMOS Gates Snapshot**

High noise margins : V OH and OL are at DD GND , respectively. No static power consumption There never exists a direct path between SS ( ) in steady-state mode . Comparable rise and fall times: (under appropriate sizing conditions) La logica combinatoria

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**La logica combinatoria**

CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors La logica combinatoria

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**La logica combinatoria**

Switch Delay Model A Req Rp Rn CL B Cint NAND2 INV NOR2 La logica combinatoria

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**Input Pattern Effects on Delay**

Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 Rp/2 CL one input goes low delay is 0.69 Rp CL High to low transition both inputs go high delay is Rn CL CL B Rn A Rp Cint La logica combinatoria

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**Delay Dependence on Input Patterns**

Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 A=B=10 45 A=1, B=10 80 A= 10, B=1 81 A=B=10 A=1 0, B=1 Voltage [V] A=1, B=10 time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF La logica combinatoria

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**La logica combinatoria**

Transistor Sizing CL B Rn A Rp Cint 2 1 4 La logica combinatoria

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**Transistor Sizing a Complex CMOS Gate**

OUT = D + A • (B + C) D A B C 1 2 4 8 6 3 La logica combinatoria

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**Fan-In Considerations**

B C D CL A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. C3 B C2 C C1 D La logica combinatoria

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**tp as a Function of Fan-In**

tpLH tp (psec) fan-in Gates with a fan-in greater than 4 should be avoided. tpHL quadratic linear tp La logica combinatoria

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**tp as a Function of Fan-Out**

tpNOR2 tp (psec) eff. fan-out All gates have the same drive current. tpNAND2 tpINV Slope is a function of “driving strength” La logica combinatoria

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**tp as a Function of Fan-In and Fan-Out**

Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO La logica combinatoria

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**Fast Complex Gates: Design Technique 1**

Transistor sizing as long as fan-out capacitance dominates Progressive sizing InN CL C3 C2 C1 In1 In2 In3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the mos closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks La logica combinatoria

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**Fast Complex Gates: Design Technique 2**

Transistor ordering C2 C1 In1 In2 In3 M1 M2 M3 CL critical path charged 1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL discharged La logica combinatoria

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**Fast Complex Gates: Design Technique 3**

Isolating fan-in from fan-out using buffer insertion CL CL La logica combinatoria

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**Fast Complex Gates: Design Technique 4**

Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) La logica combinatoria

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**Sizing Logic Paths for Speed**

Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain – can we generalize it for any type of logic? La logica combinatoria

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**La logica combinatoria**

Buffer Example For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path? CL In Out 1 2 N (in units of tinv) La logica combinatoria

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**La logica combinatoria**

Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter f(W) g – logical effort (kRunitCunit) – gate parameter f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1. La logica combinatoria

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**La logica combinatoria**

Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size La logica combinatoria

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**La logica combinatoria**

Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity La logica combinatoria

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**La logica combinatoria**

Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3 La logica combinatoria

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**La logica combinatoria**

Logical Effort of Gates La logica combinatoria

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**La logica combinatoria**

Add Branching Effort Branching effort: La logica combinatoria

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**La logica combinatoria**

Multistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D = Sdi = Spi + Shi La logica combinatoria

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**Optimum Effort per Stage**

When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g1f1 = g2f2 = … = gNfN La logica combinatoria

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**Optimal Number of Stages**

For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’ La logica combinatoria

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**La logica combinatoria**

Logical Effort From Sutherland, Sproull La logica combinatoria

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**Method of Logical Effort**

Compute the path effort: F = GBH Find the best number of stages N ~ log4F Compute the stage effort f = F1/N Sketch the path with this number of stages Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. La logica combinatoria

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**La logica combinatoria**

Summary Sutherland, Sproull Harris La logica combinatoria

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**La logica combinatoria**

Power If well designed, the dynamic power prevails P=α01 CL VDD2 α01 is activity factor = 0.5 for the inverter La logica combinatoria

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**La logica combinatoria**

Ratioed Logic La logica combinatoria

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**La logica combinatoria**

Ratioed Logic La logica combinatoria

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**La logica combinatoria**

Active Loads La logica combinatoria

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**La logica combinatoria**

Pseudo-NMOS La logica combinatoria

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**La logica combinatoria**

Pseudo-NMOS VTC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V in [V] o u t W/L p = 4 = 2 = 1 = 0.25 = 0.5 La logica combinatoria

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**La logica combinatoria**

Pass-Transistor Logic La logica combinatoria

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**La logica combinatoria**

Pass-Transistor Logic La logica combinatoria

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**La logica combinatoria**

Example: AND Gate La logica combinatoria

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**La logica combinatoria**

NMOS-Only Logic 0.5 1 1.5 2 0.0 1.0 2.0 3.0 Time [ns] V o l t a g e [V] x Out In La logica combinatoria

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**NMOS Only Logic: Level Restoring Transistor**

2 1 n r Out A B V DD Level Restorer X • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem La logica combinatoria

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**Solution 2: Transmission Gate**

B C L = 0 V A = 2.5 V C = La logica combinatoria

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**Resistance of Transmission Gate**

La logica combinatoria

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**La logica combinatoria**

Transmission Gate XOR A B F M1 M2 M3/M4 La logica combinatoria

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**Delay in Transmission Gate Networks**

V 1 i-1 C 2.5 i i+1 n-1 n In R eq (a) (b) m (c) La logica combinatoria

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**La logica combinatoria**

Delay Optimization La logica combinatoria

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**La logica combinatoria**

Dynamic Logic La logica combinatoria

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**La logica combinatoria**

Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors La logica combinatoria

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**La logica combinatoria**

Dynamic Gate In1 In2 PDN In3 Me Mp Clk Out CL A B C Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) La logica combinatoria

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**La logica combinatoria**

Dynamic Gate In1 In2 PDN In3 Me Mp Clk Out CL A B C Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 ((AB)+C) La logica combinatoria

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**La logica combinatoria**

Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL La logica combinatoria

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**Properties of Dynamic Gates**

Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL La logica combinatoria

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**Properties of Dynamic Gates**

Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock La logica combinatoria

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**Solution to Charge Leakage**

CL Clk Me Mp A B Out Mkp Same approach as level restorer for pass-transistor logic Keeper La logica combinatoria

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**Issues in Dynamic Design 2: Charge Sharing**

CL Clk CA CB B=0 A Out Mp Me Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness La logica combinatoria

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**La logica combinatoria**

Charge Sharing B = Clk X C L a b A Out M p V DD e La logica combinatoria

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**Solution to Charge Redistribution**

Clk Me Mp A B Out Mkp Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) La logica combinatoria

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**Issues in Dynamic Design 3: Backgate Coupling**

Clk Mp Out1 =1 Out2 =0 CL1 CL2 In A=0 B=0 Clk Me Dynamic NAND Static NAND La logica combinatoria

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**La logica combinatoria**

Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) La logica combinatoria

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**Cascading Dynamic Gates**

Clk Out1 In Mp Me Out2 V t V VTn Only 0 1 transitions allowed at inputs! La logica combinatoria

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**La logica combinatoria**

Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1 1 1 0 0 0 0 1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me La logica combinatoria

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**La logica combinatoria**

Why Domino? Clk Ini PDN Inj Like falling dominos! La logica combinatoria

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**Properties of Domino Logic**

Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort La logica combinatoria

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**Designing with Domino Logic**

p e V DD PDN Clk In 1 2 3 Out1 4 Out2 r Inputs = 0 during precharge Can be eliminated! La logica combinatoria

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**La logica combinatoria**

Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage La logica combinatoria

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**Differential (Dual Rail) Domino**

B Me Mp Clk Out = AB !A !B Mkp Solves the problem of non-inverting logic on off La logica combinatoria

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**La logica combinatoria**

np-CMOS In1 In2 PDN In3 Me Mp Clk Out1 In4 PUN In5 Out2 (to PDN) 1 1 1 0 0 0 0 1 Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN La logica combinatoria

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Mary Jane Irwin ( ) Modified by Dr. George Engel (SIUE)

Mary Jane Irwin ( ) Modified by Dr. George Engel (SIUE)

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