1. Lecture #25 Timing issues
10/29/2004
EE 42 fall 2004 lecture 25

2. Topics Today: Gate delays Timing diagrams Glitches Reading: Handout
10/29/2004
EE 42 fall 2004 lecture 25

3. Alternative reading Schwarz and Oldham
Electrical Engineering, an Introduction
Second edition
Saunders College publishing
Available used in campus bookstores
Recommended Chapters:
1-5Circuits
13,15transistors
11Digitial circuits
12Digital systems
10/29/2004
EE 42 fall 2004 lecture 25

4. Transistor Inverter Example
It may be simpler to just think of PMOS and NMOS transistors instead of a general 3 terminal pull-up or pull-down devices or networks.
VIN-D
Pull-Down
Network
VOUT
IOUT
Output
VDD
Pull-Up
VIN-U
VIN-D
VIN-U
VOUT
IOUT
Output
VDD
p-type MOS
Transistor
(PMOS)
n-type MOS
(NMOS)
10/29/2004
EE 42 fall 2004 lecture 25

5. Complementary Networks
If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.
The reverse is also true.
Determining the logic function from CMOS circuit is not hard:
Look at the NMOS half. It will tell you when the output is logic zero.
Parallel transistors: “like or”
Series transistors: “like and”
10/29/2004
EE 42 fall 2004 lecture 25

6. Resistance and Capacitance
VGS > VTH(n)
gate - +
drain
metal
metal
oxide insulator
metal
n-type _ _ _ e e e _ e e
n-type + + + _ + + + _ _ _ _
p-type h h h h h h h h h h
metal
The separation of charge by the oxide insulator creates a natural capacitance in the transistor from gate to source.
The silicon through which ID flows has a natural resistance.
There are other sources of capacitance and resistance too.
10/29/2004
EE 42 fall 2004 lecture 25

7. Gate Delay e e Suppose VIN abruptly changed from logic 0 to logic 1.
VDD
VOUT1 D S
VDD
VOUT2 e
VIN e
Suppose VIN abruptly changed from logic 0 to logic 1.
VOUT1 may not change quickly, since is attached to the gates of the next inverter.
These gates must collect/discharge electrons to change voltage.
Each gate attached to the output contributes a capacitance.
10/29/2004
EE 42 fall 2004 lecture 25

8. Gate Delay—The Full PictureS
VDD
VOUT1 D S
VDD
VOUT2 e
VIN e
Where will these electrons come from/go to?
No charges can pass through the cutoff transistor.
Charges will go through the pull-down/pull-up transistors to ground. These transistors contribute resistance.
10/29/2004
EE 42 fall 2004 lecture 25

9. Computing Gate Delay tp = (ln 2)RC D S VDD VOUT1 D S VDD VOUT2 VIN
1. Determine the capacitance of each gate attached to the output. These combine in parallel. Higher fan-out = more capacitance.
2. Determine which transistors are pulling-up or pulling-down the output. Each contributes a resistance, and may need to be combined in series and/or parallel.
3. The C from 1) and R from 2) are the RC for the VOUT1 transition.
10/29/2004
EE 42 fall 2004 lecture 25

10. Example Logic 0 = 0 V Logic 1 = 1 V NMOS resistance Rn = 1 kW
Suppose we have the following circuit:
If A and B both transition from
logic 1 to logic 0 at t = 0,
find the voltage at the NAND
output, VOUT(t), for t ≥ 0.
Logic 0 = 0 V
Logic 1 = 1 V
NMOS resistance
Rn = 1 kW
PMOS resistance
Rp = 2 kW
Gate capacitance
CG = 50 pF
10/29/2004
EE 42 fall 2004 lecture 25

11. Answer VOUT(t) = 0 + (1-0) e-t/(2 kW 200 pF) V
VOUT(t) = e-t/(400 ns) V
A and B both transition from 0 to 1. Since VOUT comes out of a NAND of A with B, VOUT transitions from 1 to 0.
VOUT(0) = 1 V VOUT,f = 0 V
Since the output is transitioning from 1 to 0, it is being pulled down. Both NMOS transistors in the NAND were previously cutoff, but are now active. The NMOS in the NAND are in series, so the resistances add:
R = 2 RN = 2 kW
The output in question feeds into 2 logic gate inputs (one inverter, one NOR). Each CMOS input is attached to two transistors. Thus we have 2 x 2 = 4 gate capacitances to charge. All capacitances are in parallel, so they add:
C = 4 CG = 200 pF
10/29/2004
EE 42 fall 2004 lecture 25

12. Case #1: VIN = VDD = 5V The Output is Pulled-Down
VOUT
IOUT
Output
VIN-D
VDD
VIN-U
p-type MOS
Transistor
(PMOS)
n-type MOS
(NMOS)
VIN = VDD = 5V
The PMOS transistor is OFF when VIN > VDD-VTU
The NMOS transistor is ON when VIN > VTD
VOUT(V) 3 5
IOUT(mA) 20 60
100
VIN = 5
10/29/2004
EE 42 fall 2004 lecture 25

13. Case #2: VIN = 0 The Output is Pulled-Up
VOUT(V) 3 5
IOUT(mA) 20 60
100
VIN=1V
VOUT
IOUT
Output
VIN-D
VDD
VIN-U
p-type MOS
Transistor
(PMOS)
n-type MOS
(NMOS)
VIN = 0
The PMOS transistor is ON when VIN < VDD-VTU
The NMOS transistor is OFF when VIN < VTD
10/29/2004
EE 42 fall 2004 lecture 25

14. How many “gate delays for shortest path? ANSWER : 2
EFFECT OF GATE DELAY
Cascade of Logic Gates A B C D
Inputs have different delays, but we ascribe a single worst-case delay  to every gate
How many “gate delays for shortest path?
ANSWER : 2
How many gate delays for longest path?
ANSWER : 3
10/29/2004
EE 42 fall 2004 lecture 25

15. Timing diagrams
To show the time at which logic signals change, a timing diagram is used. For combinatorial logic, the diagram will just show gate delays and glitches
AND gate: A B
A•B
10/29/2004
EE 42 fall 2004 lecture 25

16. Glitching: temporary switching to an incorrect value
TIMING DIAGRAMS
Glitching: temporary switching to an incorrect value
Show transitions of variables vs time A
Logic state B D 1 t C
Note becomes valid one gate delay after B switches t t
Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. t t 2t t t
No change at t = 3t t t 2t 3t
10/29/2004
EE 42 fall 2004 lecture 25

17. Inverter Propagation Delay
Discharge (pull-down)
VOUT
VDD
VIN = Vdd
COUT = 50fF
VOUT
VDD
VIN = Vdd RD
COUT = 50fF
Dt = 0.69RDCOUT = 0.69(10kW)(50fF) = 345 ps
Discharge (pull-up)
Dt = 0.69RUCOUT = 0.69(10kW)(50fF) = 345 ps
10/29/2004
EE 42 fall 2004 lecture 25

18. CMOS Logic Gate NMOS and PMOS use the same set of input signals VDDB C
VDD
VOUT
PMOS only in pull-up
PMOS conduct when input is low
PMOS do not conduct when A +(BC)
NMOS only in pull-down
NMOS conduct when input is high.
NMOS conduct for A + (BC)
Logic is Complementary and produces F = A + (BC)
10/29/2004
EE 42 fall 2004 lecture 25

19. CMOS Logic Gate: Example InputsB C
VDD
VOUT
A = 0
B = 0
C = 0
PMOS all conduct
Output is High
= VDD
NMOS do not conduct
Logic is Complementary and produces F = 1
10/29/2004
EE 42 fall 2004 lecture 25

20. CMOS Logic Gate: Example InputsB C
VDD
VOUT
A = 0
B = 1
C = 1
PMOS A conducts; B and C Open
Output is High
= 0
NMOS B and C conduct; A open
Logic is Complementary and produces F = 0
10/29/2004
EE 42 fall 2004 lecture 25

21. Switched Equivalent Resistance NetworkB C
VDD
VOUT RU RD A B C
VDD
VOUT
Switches close when input is low.
Switches close when input is high.
10/29/2004
EE 42 fall 2004 lecture 25

22. Logic Gate Propagation Delay: Initial StateB C
VDD
VOUT RU RD
COUT = 50 fF
The initial state depends on the old (previous) inputs.
The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.
Example: A=0, B=0, C=0 for a long time.
These inputs provided a path to VDD for a long time and the capacitor has precharged up to VDD = 5V.
10/29/2004
EE 42 fall 2004 lecture 25

23. Logic Gate Propagation Delay: TransientB C
VDD
VOUT RU RD
COUT = 50 fF
At t=0, B and C switch from low to high (VDD) and A remains low.
This breaks the path from VOUT to VDD
And opens a path from VOUT to GND
COUT discharges through the pull-down resistance of gates B and C in series.
Dt = 0.69(RDB+RDC)COUT
= 0.69(20kW)(50fF) = 690 ps
The propagation delay is two times longer than that for the inverter!
10/29/2004
EE 42 fall 2004 lecture 25

24. Logic Gate: Worst Case ScenariosB C
VDD
VOUT RU RD
COUT = 50 fF
What combination of previous and present logic inputs will make the Pull-Up the fastest?
Fastest overall?
What combination of previous and present logic inputs will make the Pull-Up the slowest?
Slowest overall?
What combination of previous and present logic inputs will make the Pull-Down the fastest?
What combination of previous and present logic inputs will make the Pull-Down the slowest?
10/29/2004
EE 42 fall 2004 lecture 25

25. C2 high and A2 low makes gate 2 wait for Gate 1 output
Logic Gate Cascade
To avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks. A2 B2
VDD A1 B1
VOUT 1 C2
VOUT 2
50 fF
B2 = VOUT 1
The four independent input are A1, B1, A2 and C2.
A2 high discharges gate 2 without even waiting for the output of gate 1.
C2 high and A2 low makes gate 2 wait for Gate 1 output
10/29/2004
EE 42 fall 2004 lecture 25