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1 CMOS Circuits

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2 Combination and Sequential

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3 Static Combinational Network PMOS Network NMOS Network Inputs Output VDD CMOS Circuits Pull-up network-PMOS Pull-down network- NMOS Networks are complementary to each other When the circuit is dormant, no current flows between supply lines. Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs. Output load is capacitive

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4 NAND Gates Transistors in Parallel 1/Rch eff = (1/Rch 1 ) + (1/Rch 2 ) Transistors in Series Rch eff = Rch 1 + Rch 2

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5 CMOS NAND Gate DC Analysis Two possible scenarios: 1. Both inputs are toggling 2. One input is toggling, the other one set high Assumptions: MP2=MP1=MP MN1=MN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Inverter VTC

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6 Gate Sizing To obtain equal Rise and Fall time, Size the series / parallel transistors to have an equivalent of a single PU or PD inverter transistor in your design

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7 Sizing the CMOS Gate

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8 NAND Gates: Analysis Scenario #1- Both inputs are toggling L-H > (W/L)eff = 2(W/L)p H-L > (W/L)eff = 1/2(W/L)n K R | NAND = 1/4 K R | INV Scenario #2- One input is toggling L-H > (W/L)eff = (W/L)p H-L > (W/L)eff = 1/2(W/L)n K R | NAND = 1/2 K R | INV Vout Vin V OH V OL Vx2 Vx1 Vin=Vout Inverter One input toggling Two inputs toggling

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9 NAND Gates: Analysis Switching Analysis Scenario #1- Both inputs are toggling t PLH | NAND = 1/2t PLH | INVERTER t PHL | NAND = 2t PHL | INVERTER Scenario #2- One input is toggling t PLH | NAND = t PLH | INVERTER t PHL | NAND = 2t PHL | INVERTER

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10 NAND Gate: Power Dissipation P ac = α.f. C V DD 2 A B X α = P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0 α = (1/4). (3/4)= 3/16 C = C L + C parasitic

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11 Increasing the inputs

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12 NOR Gate: Analysis DC Analysis/ AC Analysis Two possible scenarios: 1. Both inputs are toggling (one is set low) 2. One input is toggling, the other one set high Assumptions: AP2=BP1=MP AN1=BN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Compare with a CMOS inverter: MP/MN K R, and the shift in VTC Propagation delay t PLH and t PHL

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13 4 INPUT NOR Gate VDD A B C D A B C D C L X Very slow rise time and rise delays Could be compensated by increasing of PMOS transistor size. Implications: Silicon Area Input capacitance

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14 Practical Considerations 1. Minimize the use of NOR gates 2. Minimize the fan-in of NOR gates 3. Limit the fan-in to 4 for NAND gates 4. Use De morgans theorem to reduce the number of fan-in per gate Example:

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15 Complex CMOS Gate

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16 Reducing Output Capacitance

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17 Pseudo nMOS

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18 Pseudo nMOS NAND/NOR Gates From Lecture #4 For acceptable operation WN=1.5 WP for our Process respecting min WP

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19 Pseudo nMOS Complex Gates From Lecture #4 For acceptable operation WN=1.5 WP for our Process respecting min WP

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20 CASCODE LOGIC Lad is cross coupled pMOS transistors Logic is series and parallel complementary transistors Input and Output are in Complementary forms

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21 CSACODE Inverter/Nand Gate

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22 CASCODE Complex Gate

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23 DCVS trees for a full adder Sum and Carry Pull- Down Networks S(A,B,C) = ABC + ABC + ABC + ABC C(A,B,C) = AB + BC + AC

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24 Transmission Gate Bi-directional switch, passes digital signals Less complex and more versatile than AND gate Passes analog signals Problems: Large ON resistance during transitions of input signals Large input and output capacitance (useful for data storage applications) Capacitive coupling Applications: Multiplexers, encoders, latches, registers various combinational logic circuits C C AB

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25 NMOS/PMOS as Pass Transistors ViVo C CL NMOS Transistor Passes weak 1 signal Vo = V DD -V TN Passes 0 signal undegraded Vo Vi V DD -V TN ViVo C CL V DD -V TN Vo Vi -V TP PMOS Transistor Passes 1 signal undegraded Passes weak 0 signal Vo= -V TP

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26 TX Gate: Characteristics Vo Vin 0V |V TP | V DD -V TN V DD nmos:lin nmos:sat nmos:off pmos:sat pmos:lin pmos:lin 0

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27 AND, NAND ABF

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28 OR, NOR ABF

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29 A multiplexer CABFCABF

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30 XOR ABF

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31 Four to one multiplexer

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32 TX Gate: Layout VDD VSS VO Vi C CCC For data path structure P+ N+

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33 NAND Gates: Layout Layout Transistors in Series Transistors in Parallel

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34 NAND Gates: Layout A B X Metal II Via VDD GND

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35 NOR Gate: Layout AB X V DD GND

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36 Analysis and Design of Complex Gate A B C D E F VDD GND OUT N-well Analysis 1. Construct the schematic 2. Determine the logic function. 3. Determine transistor sizes. 4. Determine the input pattern to cause slowest and fastest operations. 5. Determine the worst case rise delay (t PLH )and fall delay (t PHL ) 6. Determine the best case rise and fall delays.

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