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EE415 VLSI Design COMBINATIONAL LOGIC [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Presentation on theme: "EE415 VLSI Design COMBINATIONAL LOGIC [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]"— Presentation transcript:

1 EE415 VLSI Design COMBINATIONAL LOGIC [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2 EE415 VLSI Design Overview Simple complementary MOS gates Construction of complex CMOS gates VLSI cell design methodology Standard cells Stick diagrams Euler path Delays Transistor sizing Fan-in and fan-out considerations

3 EE415 VLSI Design Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

4 EE415 VLSI Design Static Complementary CMOS PUN and PDN are dual logic networks Pull-up network (PUN) and pull-down network (PDN) V DD F(In 1,In 2,…In N ) In 1 In 2 In N In 1 In 2 In N PUN PDN … … PMOS transistors only pull-up: make a connection from V DD to F when F(In 1,In 2,…In N ) = 1 NMOS transistors only pull-down: make a connection from F to GND when F(In 1,In 2,…In N ) = 0

5 EE415 VLSI Design NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

6 EE415 VLSI Design PMOS Transistors in Series/Parallel Connection

7 EE415 VLSI Design Threshold Drops V DD V DD 0 PDN 0 V DD CLCL CLCL PUN V DD 0 V DD - V Tn CLCL V DD V DD |V Tp | CLCL S DS D V GS S SD D

8 EE415 VLSI Design Complementary CMOS Logic Style

9 EE415 VLSI Design Example Gate: NAND

10 EE415 VLSI Design Example Gate: NOR

11 EE415 VLSI Design Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

12 EE415 VLSI Design Constructing a Complex Gate

13 EE415 VLSI Design Cell Design l Standard Cells »General purpose logic »Can be synthesized »Same height, varying width l Datapath Cells »For regular, structured designs (arithmetic) »Includes some wiring in the cell »Fixed height and width

14 EE415 VLSI Design Standard Cell Layout Methodology – 1980s signals Routing channel V DD GND

15 EE415 VLSI Design Standard Cell Layout Methodology – 1990s M2 No Routing channels V DD GND M3 V DD GND Mirrored Cell

16 EE415 VLSI Design Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx Pitch = repetitive distance between objects Cell height is 12 pitch 2 Rails ~10 In Out V DD GND

17 EE415 VLSI Design Standard Cells In Out V DD GND InOut V DD GND With silicided diffusion With minimal diffusion routing

18 EE415 VLSI Design Standard Cells A Out V DD GND B 2-input NAND gate

19 EE415 VLSI Design Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2

20 EE415 VLSI Design Stick Diagrams j V DD X X i GND AB C PUN PDN Logic Graph C AB X = C (A + B) B A C i j A B C

21 EE415 VLSI Design ABC X V DD GND X CAB V DD GND uninterrupted diffusion strip Two Versions of C (A + B)

22 EE415 VLSI Design Consistent Euler Path j V DD X X i GND AB C ABC An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph l Euler path: a path through all nodes in the graph such that each edge is visited once and only once.

23 EE415 VLSI Design OAI22 Logic Graph C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

24 EE415 VLSI Design Example: x = ab+cd

25 EE415 VLSI Design Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

26 EE415 VLSI Design CMOS Circuit Styles l Static complementary CMOS - except during switching, output connected to either V DD or GND via a low- resistance path »high noise margins –full rail to rail swing –V OH and V OL are at V DD and GND, respectively »low output impedance, high input impedance »no steady state path between V DD and GND (no static power consumption) »delay a function of load capacitance and transistor resistance »comparable rise and fall times

27 EE415 VLSI Design Switch Delay Model CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 A R eq A A RpRp A RpRp A RnRn CLCL INV NOR2

28 EE415 VLSI Design Input Pattern Effects on Delay l Delay is dependent on the pattern of inputs l Low to high transition »both inputs go low –delay is 0.69 R p /2 C L »one input goes low –delay is 0.69 R p C L l High to low transition »both inputs go high –delay is R n C L CLCL B RnRn A RpRp B RpRp A RnRn C int

29 EE415 VLSI Design Delay Dependence on Input Patterns A=B=1 0 A=1, B=1 0 A=1 0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B= A=1, B= A= 0 1, B=1 61 A=B= A=1, B= A= 1 0, B=1 81 NMOS = 0.5 m/0.25 m PMOS = 0.75 m/0.25 m C L = 100 fF

30 EE415 VLSI Design Transistor Sizing CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL

31 EE415 VLSI Design Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

32 EE415 VLSI Design Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

33 EE415 VLSI Design t p as a Function of Fan-In t pL H t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided. t pHL quadratic linear tptp

34 EE415 VLSI Design t p as a Function of Fan-Out t p NOR2 t p (psec) eff. fan-out All gates have the same drive current. t p NAND2 t p INV Slope is a function of driving strength

35 EE415 VLSI Design Problems with Complementary CMOS Gate with N inputs requires 2N transistors other circuit styles use N+1 transistors t p deteriorates with high fan-in increases total capacitance series connected transistors slow down gate fan-out loads down gate 1 fan-out = 2 gate capacitors (PMOS and NMOS)


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