1. PLDs
ROM : Programmable OR array
PLA : Programmable Logic Array Programmable OR – AND arrays.
PAL : Programmable Array Logic .
Programmable AND array, fixed OR
GAL : Generic Array Logic
Can be configured to emulate many earlier PLDs including those with internal Flip-Flops
CPLD : Complex PLD
FPGA : Field Programmable Gate Arrays

2. PLDs ROM : Read Only Memories
Matrix of data that is accesded one row at a time
Internaly a ROM contains a decoder and a storage array.
Functionally the data array can be viewed as a programmable OR array.
Types:
Mask programmed ROM
Field programmable ROM – PROM
Erasable ROM – EPROM
Ellectrically programmable ROM - EEROM

3. PALs and PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form

4. PALs and PLAs Key to Success: Shared Product Terms Equations
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Example:
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Personality Matrix
Output Side:
1 = term connected to output
0 = no connection to output

5. All possible connections are available
PALs and PLAs
Example Continued
All possible connections are available
before programming

6. PALs and PLAs Example Continued Unwanted connections are "blown"
Note: some array structures
work by making connections
rather than breaking them

7. Notation for implementing
PALs and PLAs
Alternative representation for high fan-in structures
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D

8. PALs and PLAs Design Example Multiple functions of A, B, C F1 = A B C
F5 = A xor B xor C
F6 = A xnor B xnor C

9. PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept — implemented by Monolithic Memories
constrained topology of the OR Array
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept — generalized topologies in AND and OR planes
The main advantage of the PAL over the Pla and the ROM is that it is faster

10. PALs and PLAs Design Example: BCD to Gray Code Converter Truth Table
K-maps
Minimized Functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'

11. PALs and PLAs
Programmed PAL:
4 product terms per each OR gate

12. PALs and PLAs Code Converter Discrete Gate Implementation
4 SSI Packages vs. 1 PLA/PAL Package!

13. PALs and PLAs
Another Example: Magnitude Comparator

14. PALs and PLAs EXAMPLES Typical First Generation PAL : 16L8
10 input, 2 complemented output, 6 I/O pins
Programmable (one AND term) 3- state outputs
Seven product terms per output
20 pin chip
GAL 16V8C and 20V8C ( 20 pins and 24 pins)
10 input (14 for 20V8)
Programmable (one AND term) 3-state outputs
Seven or eigth product terms per output
Programmable output polarity
Three combinational ouputs configurations: Bidir I/O , dedicated output , dedicated input.
GAL 22V10C
24 pin chip, 12 input terminals and 10 I/O terminals
Two of the outputs can have up to 8 product terms, two have 10, two have 12, two have 14 and two have 16,
not counting the ouput buffer control.
Combinational configurations.

15. Combinational Logic Word Problems
BCD to 7 Segment Display Controller
Understanding the problem:
input is a 4 bit bcd digit
output is the control signals for the display
4 inputs A, B, C, D
7 outputs C0 — C6
Block Diagram

16. BCD to 7 Segment Display Controller
C0 = A + B D + C + B' D'
C1 = A + C' D' + C D + B'
C2 = A + B + C' + D
C3 = B' D' + C D' + B C' D + B' C
C4 = B' D' + C D
C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C
14 Unique Product Terms

17. BCD to 7 Segment
Display Controller
16H8PAL
Can Implement
the function

18. BCD to 7 Segment
Display Controller
14H8PAL
Cannot Implement
the function

19. BCD to 7 Segment Display Controller
PLA Implementation

20. BCD to7 Segment Display Controller
Multilevel Implementation
X = C' + D'
Y = B' C'
C0 = C3 + A' B X' + A D Y
C1 = Y + A' C5' + C' D' C6
C2 = C5 + A' B' D + A' C D
C3 = C4 + B D C5 + A' B' X'
C4 = D' Y + A' C D'
C5 = C' C4 + A Y + A' B X
C6 = A C4 + C C5 + C4' C5 + A' B' C
52 literals
33 gates
Ineffective use of don't cares

21. Implementation Strategies
More Advanced PAL Architectures
Registered PAL Architecture
Buffered Input
or product term
Negative Logic
Feedback
D2 = Q2 • Q0 + Q2 • Q0
D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X • Q1 + X • Q1

22. Implementation Strategies
Advanced PAL Architectures
Programmable Output Polarity/XOR PALs
Buried Registers: decouple
FF from the output pin
Advantage of XOR PALs: Parity and Arithmetic Operations

23. Implementation Strategies
Example of XOR PAL
Example of Registered PAL

24. Implementation Strategies
FSM Design with More Sophisticated PLDs
CPLDs
Increasing the size of a conventional PAL or GAL is not an
effective way to increase complexity.
Several PALs on one chip.
Xilinx 9500-series : PLDs have 18 output macrocells,
CPLDs have from 2 to 16 PLDs
Packages have from 44 to 352 pins
Programmable Logic Devices = PLD
PALs, PLAs = Gate Equivalents
Field Programmable Gate Arrays = FPGAs (CLB:Configurable Logic Block)
• Altera MAX Family
• Actel Programmable Gate Array
• Xilinx Logical Cell Array
(s) of Gate Equivalents!

25. Programmable feedback
Implementation Strategies
Design with More Sophisticated PLDs
Altera EPLD (Erasable Programmable Logic Devices)
Historical Perspective:
PALs – same technology as programmed once bipolar PROM
EPLDs — CMOS erasable programmable ROM (EPROM)
erased by UV light
Altera building block = MACROCELL
8 Product Term
AND-OR Array +
Programmable
MUX's
I/O Pin
Seq. Logic
Block
Programmable polarity
Programmable feedback

26. Implementation Strategies
Design with More Sophisticated PLDs
Altera EPLDs contain 8 to 48 independently programmed macrocells
Personalized by EPROM bits:
Flipflop controlled
by global clock signal
local signal computes
output enable
Flipflop controlled
by locally generated
clock signal
+ Seq Logic: could be D, T positive or negative edge triggered
+ product term to implement clear function

27. Implementation Strategies
Design with More Sophisticated PLDs
AND-OR structures are relatively limited
Cannot share signals/product terms among macrocells
Altera solution: Multiple Array Matrix (MAX)
Logic
Array
Blocks
(similar to
macrocells)
Global Routing:
Programmable
Interconnect
Array
EPM5128:
8 Fixed Inputs
52 I/O Pins
8 LABs
16 Macrocells/LAB
32 Expanders/LAB

28. Implementation Strategies
Design with More Sophisticated PLDs
LAB Architecture
Expander Terms shared among all
macrocells within the LAB