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**Memory and Programmable Logic**

Chapter 7

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**7-1 Introduction Memory RAM – Random-Access Memory**

information storage a collection of cells store binary information RAM – Random-Access Memory read operation write operation ROM – Read-Only Memory read operation only a programmable logic device

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**Programmable Logic Device (PLD)**

ROM PLA – programmable logic array PAL – programmable array logic FPGA – field-programmable gate array programmable logic blocks programmable interconnects Fig. 7.1 Conventional and array logic diagrams for OR gates

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**7-2 Random-Access Memory**

A memory unit stores binary information in groups of bits (words) 8 bits (a byte), 2 bytes, 4 bytes Block diagram Fig. 7.2 Block diagrams of a memory unit

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A 1024 16 Memory Fig. 7.3 Contents of a 1024 16 memory

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**Write and Read Operations**

Write operation Apply the binary address to the address lines Apply the data bits to the data input lines Activate the write input Read operation Activate the read input

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**Memory Description in HDL**

Examples

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HDL Example 7.1

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Timing Waveforms The operation of the memory unit is controlled by an external device The access time the time required to select a word and read it The cycle time the time required to complete a write operation Read and write operations must synchronized with an external clock

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**The access/cycle time < 50 ns A write cycle**

CPU clock – 50 MHz The access/cycle time < 50 ns A write cycle Fig. 7.4 Memory cycle timing waveforms

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A read cycle Fig. 7.4 Memory cycle timing waveforms (cont.)

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**Types of Memories Static Dynamic Information are stored in latches**

remains valid as long as power is applied short read/write cycle Dynamic Information are stored in the form of charges on capacitors the stored charge tends to discharge with time need to be refreshed (read and write back) reduced power consumption Larger memory capacity

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**Volatile Non-volatile lose stored information when power is turned off**

SRAM, DRAM Non-volatile Retains its stored information after the removal of power ROM EPROM, EEPROM Flash memory

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**7-3 Memory Decoding A memory unit A memory cell the storage components**

the decoding circuits to select the memory word A memory cell Fig. 7.5 Memory cell

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**Internal Construction**

A RAM of m words and n bits per word m*n binary storage cells Decoding circuits to select individual words k-to-2k decoder

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A 4 4 RAM Fig. 7.6 Diagram of a 4 4 RAM

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**Coincident Decoding A two-dimensional selection scheme**

reduce the complexity of the decoding circuits Fig. 7.7 Two-dimensional decoding structure for a 1K-word memory

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**Reduce the circuit complexity and the cycle time**

A 10-to-1024 decoder 1024 AND gates with 10 inputs per gates Two 5-to-32 decoders 2 * (32 AND gates with 5 inputs per gates) Reduce the circuit complexity and the cycle time

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**Address Multiplexing To reduce the number of pins in the IC package**

consider a 64M1 DRAM 26-bit address lines Multiplex the address lines in one set of address input pins

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**An examples RAS – row address strobe CAS – column address strobe**

Fig. 7.8 Address multiplexing for a 64K DRAM

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**Random Access Memory 第三版內容，參考用! RAS, CAS Addressing**

Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs

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**Random Access Memory 第三版內容，參考用! Write Cycle Timing**

(1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle

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**7-4 Error Detection And Correction**

Improve the reliability of a memory unit A simple error detection scheme a parity bit (Sec. 3-9) a single bit error can be detected, but cannot be corrected An error-correction code generates multiple parity check bits the check bits generate a unique pattern, called a syndrome the specific bit in error can be identified

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**Hamming Code k parity bits are added to an n-bit data word**

(2k –1 n + k) The bit positions are numbered in sequence from 1 to n + k Those positions numbered as a power of 2 are reserved for the parity bits The remaining bits are the data bits

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**Example: 8-bit data word 11000100**

Include 4 parity bits and the 8-bit word 12 bits 2k –1 n + k, n = 8 k = 4 Bit position: P1 P2 1 P P Calculate the parity bits: even parity assumption P1 = XOR of bits (3, 5, 7, 9, 11) = 1 1 0 0 0 = 0 P2 = XOR of bits (3, 6, 7, 10, 11) = 1 0 0 1 0 = 0 P4 = XOR of bits (5, 6, 7, 12) = 1 0 0 0 = 1 P8 = XOR of bits (9, 10, 11, 12) = 0 1 0 0 = 1 Store the 12-bit composite word in memory.

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**When the 12 bits are read from the memory**

Check bits are calculated C1 = XOR of bits (1, 3, 5, 7, 9, 11) C2 = XOR of bits (2, 3, 6, 7, 10, 11) C4 = XOR of bits (4, 5, 6, 7, 12) C8 = XOR of bits (8, 9, 10, 11, 12) If no error has occurred Bit position: C = C8C4C2C1 = 0000

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**One-bit error Two-bit error error in bit 1 error in bit 5**

C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1 C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0 C4 = XOR of bits (4, 5, 6, 7, 12) = 0 C8 = XOR of bits (8, 9, 10, 11, 12) = 0 C8C4C2C1 = 0001 error in bit 5 C8C4C2C1 = 0101 Two-bit error errors in bits 1 and 5 C8C4C2C1 = 0100

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**The Hamming code can be used for data of nay length**

k check bits 2k –1 n + k

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**Single-Error Correction, Double-Error Detection**

Hamming code Can detect and correct only a single error Multiple errors may not be detected. Hamming code + a parity bit Can detect double errors and correct a single error. The additional parity bit is the XOR of all the other bits. E.g.: the previous 12-bit coded word P13 (even parity).

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**When the word is read from memory**

If P = 0 (XOR of all bits includes parity bits), the parity is correct; P = 1, incorrect Four cases If C = 0, P = 0, no error If C 0, P = 1, a single error that can be corrected If C 0, P = 0, a double error that is detected but cannot be corrected If C = 0, P = 1, an error occurred in the P13 bit

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**7-5 Read-Only Memory Store permanent binary information 2k x n ROM**

k address input lines enable input(s) three-state outputs Fig. 7.9 ROM block diagram

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**32 x 8 ROM 5-to-32 decoder 8 OR gates**

each has 32 inputs 32x8 internal programmable connections Fig. 7.10 Internal logic of a 32 8 ROM

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**programmable interconnections**

close (two lines are connected) or open A fuse that can be blown by applying a high voltage pulse Fig. 7.11 Programming the ROM according to Table 7.3

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**ROM truth table (partial)**

an example

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**Combinational Circuit Implementation**

ROM: a decoder + OR gates sum of minterms a Boolean function = sum of minterms For an n-input, m-output combinational ckt 2n m ROM Design procedure: Determine the size of ROM Obtain the programming truth table of the ROM The truth table = the fuse pattern

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Example 7-1 3 inputs, 6 outputs B1=0 B0=A0 8x4 ROM

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**ROM implementation Truth table Fig. 7.12**

ROM implementation of Example 7.1

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**Types of ROM Types of ROM mask programming ROM PROM: Programmable ROM**

IC manufacturers is economical only if large quantities PROM: Programmable ROM fuses universal programmer EPROM: erasable PROM floating gate ultraviolet light erasable EEPROM: electrically erasable PROM longer time is needed to write flash ROM limited times of write operations

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**Combinational PLDs Programmable two-level logic**

an AND array and an OR array Fig. 7.13 Basic configuration of three PLDs

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**7.6 Programmable Logic Array**

PLA an array of programmable AND gates can generate any product terms of the inputs an array of programmable OR gates can generate the sums of the products more flexible than ROM use less circuits than ROM only the needed product terms are generated

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An example F1 = AB + AC + ABC F2 = (AC + BC) XOR gates can invert the outputs Fig. 7.14 PLA with three inputs, four product terms, and two outputs

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PLA programming table specify the fuse map

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**When implementing with a PLA**

The size of a PLA The number of inputs The number of product terms (AND gates) The number of outputs (OR gates) When implementing with a PLA reduce the number of distinct product terms the number of terms in a product is not important

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**Examples 7-2 Fig. 7.15 Solution to Example 7.2**

F1(A, B, C) = (0, 1, 2, 4); F2(A, B, C) = (0, 5, 6, 7) both the true value and the complement of the function should be simplified to check Fig. 7.15 Solution to Example 7.2

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**PLA with three inputs, four product terms, and two outputs**

F1 = (AB + AC + BC) F2 = AB + AC + ABC Fig. 7.14 PLA with three inputs, four product terms, and two outputs

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**7-7 Programmable Array Logic**

a programmable AND array and a fixed OR array The PAL is easier to program, but is not as flexible as the PLA 第三版圖片，參考用!

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**An example PAL product terms cannot be shared Fig. 7.16**

PAL with four inputs, four outputs, and a three-wide AND-OR structure

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**An example implementation**

w(A,B,C,D) = (2,12,13) x(A,B,C,D) = (7,8,9,10,11,12,13,14) y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = (1,2,8,12,13) Simplify the functions w = ABC + ABCD x = A + BCD y = AB + CD + BD z = ABC + ABCD + ACD + ABCD = w + ACD + ABCD

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PAL programming table

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**Fuse map for PAL as specified in Table 7.6**

w = ABC + ABCD x = A + BCD y = AB + CD + BD z = w + ACD + ABCD Fig. 7.17 Fuse map for PAL as specified in Table 7.6

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**7-8 Sequential Programmable Devices**

Sequential programmable logic device SPLD PLD + filp-flops Fig. 7.18 Sequential programmable logic device

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Macrocell A typical SPLD contains 8-10 macrocells Fig. 7.19 Basic macrocell logic

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**Programming features:**

AND array use or bypass the flip-flop select clock edge polarity preset or clear for the register complement an output programmable input/output pins

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**Programmable feedback**

Altera macrocell 第三版內容，參考用! 8 Product Term AND-OR Array + Programmable MUX's I/O Pin Seq. Logic Block Programmable polarity Programmable feedback

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**Complex PLD Put a lot of PLDS on a chip**

Add wires between them whose connections can be programmed Use fuse/EEPROM technology Fig. 7.20 General CPLD configuration

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**Field-Programmable Gate Array**

Emulate gate array technology Hence Field Programmable Gate Array You need: A way to implement logic gates A way to connect them together PALs, PLAs = Gate Equivalents Field Programmable Gate Arrays = FPGAs (s) of Gate Equivalents

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**Field-Programmable Gate Arrays**

Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been fabbed 第三版內容，參考用!

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**Basic Xilinx Architecture**

Fig. 7.21 Basic architecture of Xilinx Spartan and predecessor devices

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**Configurable Logic Block (CLB)**

CLB architecture

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**Interconnect Resources**

Fig. 7.23 RAM cell controlling a PIP transition gate

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**Programmable Interconnect Point (PIP)**

Fig. 7.24 Circuit for a programmable PIP

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I/O Block (IOB) Fig. 7.25 XC4000 series IOB

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Enhancements Fig. 7.26 Distributed RAM cell formed from a lookup table

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**Xilinx Spartan XL FPGAs**

Fig. 7.27 Spartan dual-port RAM

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**Xilinx Spartan XL FPGAs**

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**Xilinx Spartan II FPGAs**

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**Xilinx Spartan II FPGAs**

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**Xilinx Spartan II FPGAs**

Fig. 7.28 Spartan II architecture

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**Xilinx Spartan II FPGAs**

Fig. 7.29 Spartan II CLB slice

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**Xilinx Spartan II FPGAs**

Fig. 7.30 Spartan II IOB

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Xilinx Virtex FPGAs Fig. 7.31 Virtex II overall architecture

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Xilinx Virtex FPGAs Fig. 7.32 Virtex IOB block

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