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Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.

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Presentation on theme: "Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information."— Presentation transcript:

1 Memory and Programmable Logic Chapter 7

2 Digital Circuits Introduction Memory information storage a collection of cells store binary information RAM – Random-Access Memory read operation write operation ROM – Read-Only Memory read operation only a programmable logic device

3 Digital Circuits 3 Programmable Logic Device (PLD) ROM PLA – programmable logic array PAL – programmable array logic FPGA – field-programmable gate array programmable logic blocks programmable interconnects Fig. 7.1 Conventional and array logic diagrams for OR gates

4 Digital Circuits Random-Access Memory A memory unit stores binary information in groups of bits (words) 8 bits (a byte), 2 bytes, 4 bytes Block diagram Fig. 7.2 Block diagrams of a memory unit

5 Digital Circuits 5 A Memory Fig. 7.3 Contents of a memory

6 Digital Circuits 6 Write and Read Operations Write operation Apply the binary address to the address lines Apply the data bits to the data input lines Activate the write input Read operation Apply the binary address to the address lines Activate the read input

7 Digital Circuits 7 Memory Description in HDL Examples

8 Digital Circuits 8 HDL Example 7.1

9 Digital Circuits 9 Timing Waveforms The operation of the memory unit is controlled by an external device The access time the time required to select a word and read it The cycle time the time required to complete a write operation Read and write operations must synchronized with an external clock

10 Digital Circuits 10 CPU clock – 50 MHz The access/cycle time < 50 ns A write cycle Fig. 7.4 Memory cycle timing waveforms

11 Digital Circuits 11 A read cycle Fig. 7.4 Memory cycle timing waveforms (cont.)

12 Digital Circuits 12 Types of Memories Static Information are stored in latches remains valid as long as power is applied short read/write cycle Dynamic Information are stored in the form of charges on capacitors the stored charge tends to discharge with time need to be refreshed (read and write back) reduced power consumption Larger memory capacity

13 Digital Circuits 13 Volatile lose stored information when power is turned off SRAM, DRAM Non-volatile Retains its stored information after the removal of power ROM EPROM, EEPROM Flash memory

14 Digital Circuits Memory Decoding A memory unit the storage components the decoding circuits to select the memory word A memory cell Fig. 7.5 Memory cell

15 Digital Circuits 15 Internal Construction A RAM of m words and n bits per word m*n binary storage cells Decoding circuits to select individual words k-to-2 k decoder

16 Digital Circuits 16 A 4 4 RAM Fig. 7.6 Diagram of a 4 4 RAM

17 Digital Circuits 17 Coincident Decoding A two-dimensional selection scheme reduce the complexity of the decoding circuits Fig. 7.7 Two-dimensional decoding structure for a 1K-word memory

18 Digital Circuits 18 A 10-to-1024 decoder 1024 AND gates with 10 inputs per gates Two 5-to-32 decoders 2 * (32 AND gates with 5 inputs per gates) Reduce the circuit complexity and the cycle time

19 Digital Circuits 19 Address Multiplexing To reduce the number of pins in the IC package consider a 64M 1 DRAM 26-bit address lines Multiplex the address lines in one set of address input pins

20 Digital Circuits 20 An examples RAS – row address strobe CAS – column address strobe Fig. 7.8 Address multiplexing for a 64K DRAM

21 Digital Circuits 21 Random Access Memory RAS, CAS Addressing Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs !

22 Digital Circuits 22 Random Access Memory (1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle Write Cycle Timing !

23 Digital Circuits Error Detection And Correction Improve the reliability of a memory unit A simple error detection scheme a parity bit (Sec. 3-9) a single bit error can be detected, but cannot be corrected An error-correction code generates multiple parity check bits the check bits generate a unique pattern, called a syndrome the specific bit in error can be identified

24 Digital Circuits 24 Hamming Code k parity bits are added to an n-bit data word (2 k –1 n + k) The bit positions are numbered in sequence from 1 to n + k Those positions numbered as a power of 2 are reserved for the parity bits The remaining bits are the data bits

25 Digital Circuits 25 Example: 8-bit data word Include 4 parity bits and the 8-bit word 12 bits 2 k –1 n + k, n = 8 k = 4 Bit position: P 1 P 2 1P 4 100P Calculate the parity bits: even parity assumption P 1 = XOR of bits (3, 5, 7, 9, 11) = = 0 P 2 = XOR of bits (3, 6, 7, 10, 11) = = 0 P 4 = XOR of bits (5, 6, 7, 12) = = 1 P 8 = XOR of bits (9, 10, 11, 12) = = 1 Store the 12-bit composite word in memory. Bit position:

26 Digital Circuits 26 When the 12 bits are read from the memory Check bits are calculated C 1 = XOR of bits (1, 3, 5, 7, 9, 11) C 2 = XOR of bits (2, 3, 6, 7, 10, 11) C 4 = XOR of bits (4, 5, 6, 7, 12) C 8 = XOR of bits (8, 9, 10, 11, 12) If no error has occurred Bit position: C = C 8 C 4 C 2 C 1 = 0000

27 Digital Circuits 27 One-bit error error in bit 1 C 1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1 C 2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0 C 4 = XOR of bits (4, 5, 6, 7, 12) = 0 C 8 = XOR of bits (8, 9, 10, 11, 12) = 0 C 8 C 4 C 2 C 1 = 0001 error in bit 5 C 8 C 4 C 2 C 1 = 0101 Two-bit error errors in bits 1 and 5 C 8 C 4 C 2 C 1 = 0100

28 Digital Circuits 28 The Hamming code can be used for data of nay length k check bits 2 k –1 n + k

29 Digital Circuits 29 Single-Error Correction, Double-Error Detection Hamming code Can detect and correct only a single error Multiple errors may not be detected. Hamming code + a parity bit Can detect double errors and correct a single error. The additional parity bit is the XOR of all the other bits. E.g.: the previous 12-bit coded word P (even parity).

30 Digital Circuits 30 When the word is read from memory If P = 0 (XOR of all bits includes parity bits), the parity is correct; P = 1, incorrect Four cases 1.If C = 0, P = 0, no error 2.If C 0, P = 1, a single error that can be corrected 3.If C 0, P = 0, a double error that is detected but cannot be corrected 4.If C = 0, P = 1, an error occurred in the P 13 bit

31 Digital Circuits Read-Only Memory Store permanent binary information 2 k x n ROM k address input lines enable input(s) three-state outputs Fig. 7.9 ROM block diagram

32 Digital Circuits x 8 ROM 5-to-32 decoder 8 OR gates each has 32 inputs 32x8 internal programmable connections Fig Internal logic of a 32 8 ROM

33 Digital Circuits 33 programmable interconnections close (two lines are connected) or open A fuse that can be blown by applying a high voltage pulse Fig Programming the ROM according to Table 7.3

34 Digital Circuits 34 ROM truth table (partial) an example

35 Digital Circuits 35 Combinational Circuit Implementation ROM: a decoder + OR gates sum of minterms a Boolean function = sum of minterms For an n-input, m-output combinational ckt 2 n m ROM Design procedure: 1.Determine the size of ROM 2.Obtain the programming truth table of the ROM 3.The truth table = the fuse pattern

36 Digital Circuits 36 Example inputs, 6 outputs B 1 =0 B 0 =A 0 8x4 ROM

37 Digital Circuits 37 ROM implementation Truth table Fig ROM implementation of Example 7.1

38 Digital Circuits 38 Types of ROM mask programming ROM IC manufacturers is economical only if large quantities PROM: Programmable ROM fuses universal programmer EPROM: erasable PROM floating gate ultraviolet light erasable EEPROM: electrically erasable PROM longer time is needed to write flash ROM limited times of write operations

39 Digital Circuits 39 Combinational PLDs Programmable two-level logic an AND array and an OR array Fig Basic configuration of three PLDs

40 Digital Circuits Programmable Logic Array PLA an array of programmable AND gates can generate any product terms of the inputs an array of programmable OR gates can generate the sums of the products more flexible than ROM use less circuits than ROM only the needed product terms are generated

41 Digital Circuits 41 An example F 1 = AB + AC + A BC F 2 = (AC + BC) XOR gates can invert the outputs Fig PLA with three inputs, four product terms, and two outputs

42 Digital Circuits 42 PLA programming table specify the fuse map

43 Digital Circuits 43 The size of a PLA The number of inputs The number of product terms (AND gates) The number of outputs (OR gates) When implementing with a PLA reduce the number of distinct product terms the number of terms in a product is not important

44 Digital Circuits 44 Examples 7-2 F 1 (A, B, C) = (0, 1, 2, 4); F 2 (A, B, C) = (0, 5, 6, 7) both the true value and the complement of the function should be simplified to check Fig Solution to Example 7.2

45 Digital Circuits 45 F 1 = (AB + AC + BC) F 2 = AB + AC + A B C Fig PLA with three inputs, four product terms, and two outputs

46 Digital Circuits Programmable Array Logic a programmable AND array and a fixed OR array The PAL is easier to program, but is not as flexible as the PLA !

47 Digital Circuits 47 An example PAL product terms cannot be shared Fig PAL with four inputs, four outputs, and a three-wide AND-OR structure

48 Digital Circuits 48 An example implementation w(A,B,C,D) = (2,12,13) x(A,B,C,D) = (7,8,9,10,11,12,13,14) y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = (1,2,8,12,13) Simplify the functions w = ABC + A B CD x = A + BCD y = A B + CD + B D z = ABC + A B CD + AC D + A B C D = w + AC D + A B C D

49 Digital Circuits 49 PAL programming table

50 Digital Circuits 50 w = ABC + A B CD x = A + BCD y = A B + CD + B D z = w + AC D + A B C D Fig Fuse map for PAL as specified in Table 7.6

51 Digital Circuits Sequential Programmable Devices Sequential programmable logic device SPLD PLD + filp-flops Fig Sequential programmable logic device

52 Digital Circuits 52 Macrocell A typical SPLD contains 8-10 macrocells Fig Basic macrocell logic

53 Digital Circuits 53 Programming features: AND array use or bypass the flip-flop select clock edge polarity preset or clear for the register complement an output programmable input/output pins

54 Digital Circuits 54 Altera macrocell 8 Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback !

55 Digital Circuits 55 Complex PLD Put a lot of PLDS on a chip Add wires between them whose connections can be programmed Use fuse/EEPROM technology Fig General CPLD configuration

56 Digital Circuits 56 Field-Programmable Gate Array Emulate gate array technology Hence Field Programmable Gate Array You need: A way to implement logic gates A way to connect them together PALs, PLAs = Gate Equivalents Field Programmable Gate Arrays = FPGAs (s) of Gate Equivalents

57 Digital Circuits 57 Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been fabbed Field-Programmable Gate Arrays !

58 Digital Circuits 58 Basic Xilinx Architecture Fig Basic architecture of Xilinx Spartan and predecessor devices

59 Digital Circuits 59 Configurable Logic Block (CLB) Fig CLB architecture

60 Digital Circuits 60 Interconnect Resources Fig RAM cell controlling a PIP transition gate

61 Digital Circuits 61 Programmable Interconnect Point (PIP) Fig Circuit for a programmable PIP

62 Digital Circuits 62 I/O Block (IOB) Fig XC4000 series IOB

63 Digital Circuits 63 Enhancements Fig Distributed RAM cell formed from a lookup table

64 Digital Circuits 64 Xilinx Spartan XL FPGAs Fig Spartan dual-port RAM

65 Digital Circuits 65 Xilinx Spartan XL FPGAs

66 Digital Circuits 66 Xilinx Spartan II FPGAs

67 Digital Circuits 67 Xilinx Spartan II FPGAs

68 Digital Circuits 68 Xilinx Spartan II FPGAs Fig Spartan II architecture

69 Digital Circuits 69 Xilinx Spartan II FPGAs Fig Spartan II CLB slice

70 Digital Circuits 70 Xilinx Spartan II FPGAs Fig Spartan II IOB

71 Digital Circuits 71 Xilinx Virtex FPGAs Fig Virtex II overall architecture

72 Digital Circuits 72 Xilinx Virtex FPGAs Fig Virtex IOB block


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