Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault simulation –Gate-level fault lists propagation (library based) –Boolean full differential based (general approach) –SSBDD based (tradeoff possibility) Concurrent fault simulation Critical path tracing Parallel critical path tracing Hierarchical fault simulation

Technical University Tallinn, ESTONIA Testide analüüs Rikete simuleerimise eesmärgid: -Arvutada rikete kate (testi kvaliteet) -Konstrueerida rikete tabel või sõnastik Rike Test Diagnostika sõnastik Testi analüüs – rikete simuleerimine Digitaal- süsteem Stiimul Reaktsioon

Technical University Tallinn, ESTONIA Faults in Digital Circuits 0110 T FaultF 5 located Fault table Test experiment Test generation Fault simulation Fault diagnosis Fault modeling Testing How many rows and columns should be in the Fault Table?

Technical University Tallinn, ESTONIA Fault simulation Goals: Evaluation (grading) of a test T (fault coverage) Guiding the test generation process Constructing fault tables (dictionaries) Fault diagnosis Generate initial T Evaluate T Sufficient fault coverage? Modify T Done YesNo Select target fault Generate test for target Fault simulate Discard detected faults Done No more faults Deterministic test generation Random test generation

Technical University Tallinn, ESTONIA Defect and Fault Propagation An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults (defects) Physical defects do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with logical fault models System Component Defect simulation Error Fault simulation Defects, faults and errors

Technical University Tallinn, ESTONIA Fault simulation Fault simulation techniques: serial fault simulation parallel fault simulation deductive fault simulation concurrent fault simulation critical path analysis parallel critical path analysis Common concepts: fault specification (fault collaps) fault insertion fault effect propagation fault discarding (dropping) Comparison of methods: Fault table Faults F i Test patterns T j Entry (i,j) = 1(0) if F i is detectable (not detectable) by T j

Technical University Tallinn, ESTONIA Single and Parallel Fault Simulation Parallel patterns Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y & 1 x1x1 x2x2 x3x3 z y Inserted stuck-at-1 fault Detected error Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y & 1 x1x1 x2x2 x3x3 z y Inserted stuck-at-1 fault Detected error Three test patterns Single pattern

Technical University Tallinn, ESTONIA Parallel Fault & Test Pattern Simulation Parallel patterns Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y & 1 x1x1 x2x2 x3x3 z y Inserted stuck-at-1 fault Detected error Parallel faults & 1 x1x1 x2x2 x3x3 z y Stuck-at-0 Stuck-at-1 Computer word Fault-free Detected error Inserted faults Three test patterns

Technical University Tallinn, ESTONIA Deductive Fault Simulation & & a c b y Fault list calculation: L a = L 4  L 5 L b = L 1  L 2 L c = L 3  L a L y = L b - L c L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Gate-level fault list propagation L a – faults causing erroneous signal on the node a L y – faults causing erroneous signal on the output node y Library of formulas for gates

Technical University Tallinn, ESTONIA Boolean derivatives Boolean function: Y = F(x) = F(x 1, x 2, …, x n ) Boolean partial derivative:

Technical University Tallinn, ESTONIA Boolean differentials dx - fault variable, dx  (0,1) dx = 1 - if the value of x has changed because of a fault Partial Boolean differential: Full Boolean differential:

Technical University Tallinn, ESTONIA Fault Simulation with Boolean Differentials & x1x1 x2x2 y {x 1  0} {x 2  1} {x 2  1, y  1} & x1x1 x2x2 y {x 1  0} {x 2  0} {x 1  0, x 2  0, y  0} 1 x1x1 x2x2 y {x 1  0} {x 2  1} {x 1  0, y  0}

Technical University Tallinn, ESTONIA Deductive Fault Simulation with BDs & & a c b y Fault list calculated: L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Macro-level fault propagation: Solving Boolean differential equation:  L k A B AB A B

Technical University Tallinn, ESTONIA Critical Path Tracing & & a c b y y Problems : & & /1 y & & y 1/ The critical path is not continuous The critical path breaks on the fan-out

Technical University Tallinn, ESTONIA Fault Simulation with Boolean Derivatives & 1 x1x1 y Detected faults vector: T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Simulation approaches: 1)Single fault simulation 2)Parallel fault simulation for a subset of test patterns (by extending bit-operations to operations with computer words) 3)Iterative fault simulation for subsets of faults (by creating transitive closures – deductive simulation and critical path tracing) 4)Parallel fault simulation for both, patterns and faults

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing & 1 x1x1 y Detected faults vector: T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Handling of fanout points: Fault simulation Boolean differential calculus x y xkxk x2x2 x1x1 F

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Handling of fan-out points in a single tree in general case: x y xkxk x2x2 x1x1 F x k+1 xnxn x x 1,h x 1,h-1 x 1,2 x 1,1 x1x1 All the Boolean operations can be carried out in parallel

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Handling of fan-out points in a network of nested trees: FyFy d y e D Ez c b C q A x B FzFz XyXy XzXz. where Two fanouts: q, x A,B,D,E – chains of Boolean derivatives All calculations can be carried out in parallel

Technical University Tallinn, ESTONIA Hierarchical Concurrent Fault Simulation High-Level component High-Level component High-Level component Sequence of patterns P: First Pattern R: Faults Set of patterns With faults P;P 1 (R 1 )…P n ( R n ) Set of patterns with faults P;P 1 (R 1 )…P m ( R m ) P: Pattern Set of patterns with faults P;P 1 (R 1 )…P n ( R n )

Technical University Tallinn, ESTONIA Hierarchical fault simulation Main ideas of the procedure: A target block is chosen This will be represented on gate level Fault simulation is carried out on the low level The faults through other blocks are propagated on the high level

Technical University Tallinn, ESTONIA Hierarchical fault simulation

Technical University Tallinn, ESTONIA Hierarchical fault simulation Definition of the complex pattern: D = {P, (P 1,R 1 ), …, (P k, R k )} P is the fault-free pattern (value) P i (i = 1,2,..., k) are faulty patterns, caused by a set of faults R i All the faults simulated causing the same faulty pattern P i are put together in one group R i R 1 - R k are the propagated fault groups, causing, correspondingly, the faulty patterns P 1 - P k

Technical University Tallinn, ESTONIA Fault Simulation with DD-s Fault propagation through a complex RT-level component q xAxA xcxc B C A D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. Decision diagram New D A to be calculated Sub-system for A A q xAxA B + C A xCxC A + C 04 xAxA A 0 xCxC A - 1 A + B

Technical University Tallinn, ESTONIA Fault Simulation with DD-s Example of high level fault simulation D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)} Final complex vector for A: D A = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)}