1. Lecture 9 Combinational Automatic Test-Pattern Generation (ATPG) Basics
Algorithms and representations
Structural vs. functional test
Definitions
Search spaces
Completeness
Algebras
Types of Algorithms
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VLSI Test: Lecture 9

2. Origins of Stuck-Faults
Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer
Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faults
Seshu & Freeman (1962) – Use of stuck-faults for parallel fault simulation
Poage (1963) – Theoretical analysis of stuck-at faults
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VLSI Test: Lecture 9

3. Functional vs. Structural ATPG
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VLSI Test: Lecture 9

4. Carry Circuit
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VLSI Test: Lecture 9

5. Functional vs. Structural (Continued)
Functional ATPG – generate complete set of tests for circuit input-output combinations
129 inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64 bit slices
Each with 27 faults (using fault equivalence)
At most 64 x 27 = faults (tests)
Takes s on 1 GHz ATE
Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %
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VLSI Test: Lecture 9

6. Definition of Automatic Test-Pattern Generator
Operations on digital hardware:
Inject fault into circuit modeled in computer
Use various ways to activate and propagate fault effect through hardware to circuit output
Output flips from expected to faulty signal
Electron-beam (E-beam) test observes internal signals – “picture” of nodes charged to 0 and 1 in different colors
Too expensive
Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode
Can shift state in, scan state out
Widely used – makes sequential test combinational
Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence
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VLSI Test: Lecture 9

7. Circuit and Binary Decision Tree
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VLSI Test: Lecture 9

8. Binary Decision Diagram
BDD – Follow path from source to sink node – product of literals along path gives Boolean value at sink
Rightmost path: A B C = 1
Problem: Size varies greatly
with variable order
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VLSI Test: Lecture 9

9. Algorithm Completeness
Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test
Untestable fault – no test for it even after entire tree searched
Combinational circuits only – untestable faults are redundant, showing the presence of unnecessary hardware
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VLSI Test: Lecture 9

10. Algebras: Roth’s 5-Valued and Muth’s 9-Valued
Good
Machine 1 X
Failing
Machine 1 X
Symbol D 0 1 X G0 G1 F0 F1
Meaning
1/0
0/1
0/0
1/1
X/X
0/X
1/X
X/0
X/1
Roth’s
Algebra
Muth’s
Additions
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VLSI Test: Lecture 9

11. Roth’s and Muth’s Higher-Order Algebras
Represent two machines, which are simulated simultaneously by a computer program:
Good circuit machine (1st value)
Bad circuit machine (2nd value)
Better to represent both in the algebra:
Need only 1 pass of ATPG to solve both
Good machine values that preclude bad machine values become obvious sooner & vice versa
Needed for complete ATPG:
Combinational: Multi-path sensitization, Roth Algebra
Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault
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VLSI Test: Lecture 9

12. Exhaustive Algorithm
For n-input circuit, generate all 2n input patterns
Infeasible, unless circuit is partitioned into cones of logic, with inputs
Perform exhaustive ATPG for each cone
Misses faults that require specific activation patterns for multiple cones to be tested
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 9

13. Detecting Stuck-at Faults
Inputs
Fault Free
Faulty Responses AB
Response
A/0
B/0
Z/0
A/1
B/1
Z/1 00 1 01 1 1 10 1 1 11 1 1 1 1

14. Sequential Circuit R 1 Q A S 2 Inputs Faulty Response Response 01 X 00FF
Faulty Response SR
Response
A/0
S/0
R/0
A/1
S/1
R/1 01 X 00 10 11

15. Types of
Testing

16. Types of Tests
The exhaustive test used to detect the faults on a 2-input AND gate is not practical for circuits with 20 or more primary inputs
Pseudo-exhaustive: exhaustive for components in the circuits
segmentation or partitioning
A random test is also viable to detect faults, but pseudo-exhaustive tests are more realistic for Stuck-at Faults
Deterministic or fault oriented tests

17. Functional Testing Exhaustive & pseudo-exhaustive testing :
Partial dependence circuits:
a circuit in which primary outputs (PO)
depend on all the primary inputs (PI)
- each output tested using 2ni inputs
(ni < n shows inputs affecting PO)

18. Functional Testing Exhaustive & pseudo-exhaustive testing Example :
x y
Exhaustive test
for each gate

19. Functional Testing
Exhaustive & pseudo-exhaustive testing Partitioning technique :
the circuit is partitioned into segments such that each segment has small number of inputs
each segment is tested exhaustively
usually inputs & output of each segment are not PIs or POs so we need to control segment inputs using PIs and observe its outputs using PO - this lead to sensitizing partitioning

20. Functional Testing
Example : Consider the following circuit :

21. Functional Testing Example: the following shows 8
input vectors to test exhaustively h.

22. Functional Testing Example: Add vectors 5 - 8 to test exhaustively g
and to test exhaustively y

23. Functional Testing Example: Add missing combinations to vectors
4 and 9 to test exhaustively x

24. Test Pattern Generation
Manufacturing test ideally would check every node in the circuit to prove it is not stuck.
Apply the smallest sequence of test vectors necessary to prove each node is not stuck.
Good observability and controllability reduces number of test vectors required for manufacturing test.
Reduces the cost of testing
Motivates design-for-test
17: Design for Testability

25. Test Example A3 A2 A1 A0 n1 n2 n3 Y Minimum set: SA1 SA0
17: Design for Testability

26. Test Example A3 {0110} {1110} A2 A1 A0 n1 n2 n3 Y Minimum set: SA1 SA0
17: Design for Testability

27. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 A0 n1 n2 n3 Y
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110} A1 A0 n1 n2 n3 Y
Minimum set:
17: Design for Testability

28. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110} A0 n1
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110} A0 n1 n2 n3 Y
Minimum set:
17: Design for Testability

29. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110}
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A0 {0110} {0111} n1 n2 n3 Y
Minimum set:
17: Design for Testability

30. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110}
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A0 {0110} {0111}
n1 {1110} {0110} n2 n3 Y
Minimum set:
17: Design for Testability

31. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110}
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100} n3 Y
Minimum set:
17: Design for Testability

32. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110}
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100}
n3 {0101} {0110} Y
Minimum set:
17: Design for Testability

33. Test Example A3 {0110} {1110} A2 {1010} {1110} A1 {0100} {0110}
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100}
n3 {0101} {0110}
Y {0110} {1110}
Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}
17: Design for Testability

34. Random-Pattern Generation
Flow chart for method
Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 9

35. Boolean Difference Symbolic Method (Sellers et al.)
g = G (X1, X2, …, Xn) for the fault site fj = Fj (g, X1, X2, …, Xn) 1 j m Xi = 0 or 1 for 1 i n
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 9

36. Boolean Difference (Sellers, Hsiao, Bearnson)
Shannon’s Expansion Theorem:
F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn)
Boolean Difference (partial derivative): Fj g
Fault Detection Requirements for g s-a-0 output fj as:
G (X1, X2, …, Xn) = 1
= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn)
= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1
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VLSI Test: Lecture 9

37. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

38. Fauult-Tolerant digital System Design
For xi s-a-0
11 week
Fauult-Tolerant digital System Design

39. Fauult-Tolerant digital System Design
xi s-a-0
xi s-a-1
11 week
Fauult-Tolerant digital System Design

40. Fauult-Tolerant digital System Design
Example 1: x1 s-a-0, T(x1 / 0 ) = ?
11 week
Fauult-Tolerant digital System Design

41. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

42. Fauult-Tolerant digital System Design
Example 2: h s-a-0, h s-a-1,
T(h / 0) = ?, T(h / 1) =? x
11 week
Fauult-Tolerant digital System Design

43. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

44. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

45. Fauult-Tolerant digital System Design
Proof (3)
11 week
Fauult-Tolerant digital System Design

46. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

47. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

48. Fauult-Tolerant digital System Design
T(G/0) = ?
11 week
Fauult-Tolerant digital System Design

49. Fauult-Tolerant digital System Design5 6 2 6 2 2 2 2 5
11 week
Fauult-Tolerant digital System Design

50. Fauult-Tolerant digital System Design
11 week
Fauult-Tolerant digital System Design

51. Fauult-Tolerant digital System Designx x ,
11 week
Fauult-Tolerant digital System Design

52. Path Sensitization Method Circuit Example
Fault Sensitization
Fault Propagation
Line Justification
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VLSI Test: Lecture 9

53. Path Sensitization Method Circuit Example
Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1
1≠ D D 1 1
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VLSI Test: Lecture 9

54. Path Sensitization Method Circuit Example
Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D 1
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VLSI Test: Lecture 9

55. Path Sensitization Method Circuit Example
Final try: path g – i – j – k – L – test found! D D 1 D D D 1 1
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VLSI Test: Lecture 9

56. Irredundant Hardware and Test Patterns
Combinational ATPG can find redundant (unnecessary) hardware
Fault Test
a sa1, b sa A = 1
a sa0, b sa A = 0
Therefore, these faults are not redundant
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VLSI Test: Lecture 10

57. Redundant Hardware and Simplification
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VLSI Test: Lecture 10

58. Redundant Fault q sa1 Copyright 2001, Agrawal & Bushnell
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VLSI Test: Lecture 10

59. Multiple Fault Masking
f sa0 tested when fault q sa1 not there
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VLSI Test: Lecture 10

60. Multiple Fault Masking Part II
f sa0 masked when fault q sa1 also present
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VLSI Test: Lecture 10

61. Intentional Redundant Implicant BC
Eliminates hazards in circuit output
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62. Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 9

63. Algorithm 7.1 Redundancy Removal
Repeat until there are no more redundant faults: {
Use ATPG to find all redundant faults;
Remove all redundant faults with non-
overlapping fault cone areas; }
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VLSI Test: Lecture 10

64. History of Algorithm Speedups
D-ALG
PODEM
FAN
TOPS
SOCRATES
Waicukauski et al.
EST
TRAN
Recursive learning
Tafertshofer et al.
Est. speedup over D-ALG
(normalized to D-ALG time) 1 7 23
292
ATPG System
ATPG System
ATPG System
ATPG System
485
25057
Year
1966
1981
1983
1987
1988
1990
1991
1993
1995
1997
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