1. TOPIC : Fault detection and fault redundancy UNIT 2 : Fault modeling Module 2.3 Fault redundancy and Fault collapsing

2. Fault detection Definition: A test vector ‘t’ detects a fault iff Z f (t) ≠ Z(t) Z(x) is the logic function of the healthy circuit and Z f (x) is the logic function of the faulty circuit. ‘x’ is the input vector. The circuit is tested by applying a sequence of test vectors T (t 1,t 2,…,t m ) and then comparing the output responses Z(t 1 ), Z(t 2 ), …,Z(t m ) with the expected output response i.e. output of the healthy circuit. Note: we will deal with combinational circuits only.

3. Contd … Assume OR bridging fault between B & C signal lines. In the healthy circuit ◦ Z1 = (A+B) ◦ Z2 = (B.C)’

4. Contd … In the faulty circuit ◦ Z1 f = A + (B+C) = (A+B+C) ◦ Z2 f = {(B+C).(B+C)}’ = (B+C)’ The test t(101) can detect this fault. For test t(101) ◦ Z1= 1, Z2 = 1 ◦ Z1 f = 1, Z2 f = 0 It can be observed that the output vector Z is 11 in the healthy circuit and is 10 in the faulty circuit. Since the outputs are different, this test vector can detect the above fault. Check whether the vectors 101, 110, 011, 111 can be used as test vectors.

5. Representing faulty value in the circuit At every node V/V f is noted down, where V is the value of the signal in the healthy circuit and V f is in the faulty circuit. At the faulty node, V and V f should be different to detect the fault In the previous example for test vector 101, the representation is:

6. Necessities to detect a fault To detect a fault with the given test ‘t’ ◦ Fault effect (fault generation), and ◦ Fault propagation, are necessary. Fault effect: At the site of fault, the test ‘t’ should create different V and V f values i.e. the test should generate an error. Fault propagation: The fault generated should be propagated to one of the primary outputs through at least one path between the fault site and primary output.

7. Fault Sensitization The test should be designed in such a way that it creates different V and V f values at the fault site and it propagates to one of the primary outputs. A line whose value in the test ‘t’ changes in the presence of the fault ‘f’ is said to be sensitized to the fault ‘f’ by test ‘t’. A path composed of sensitized lines is called a sensitized path.

8. Undetectable fault A fault ‘f’ is said to be undetectable if there exists no test ‘t’ that can detect the fault ‘f’. In this case Z f (x) = Z(x) and no test can activate ‘f’ and create a sensitized path to any primary output. A fault is said to be detectable if there exists a test that can detect the given fault. A complete test set may not be sufficient to detect all the detectable faults if an undetectable fault is present in the circuit.

9. Example Assume OR bridging fault between signal lines ‘y’ and ‘x’ Z = xy + x’z Z f = xy + yz + z’x = xy + zx’ => Z f = Z

10. How undetectable fault affects other faults Because of the undetectable stuck-at-1 at node ‘a’, fault stuck-at-0 at node ‘b’ cant be detected.

11. Redundancy A combinational circuit with an undetectable fault can be simplified by removing at least a gate or that gate input. For example, suppose if a stuck-at-1 fault at an input of n-input AND gate is undetectable, then that input can be removed. The circuit now reduces to (n-1) input AND gate. Similarly if a stuck-at-0 fault at an input of AND gate is undetectable, the gate can be replaced with a constant signal ‘0’.

12. Contd … A combinational circuit with an undetectable fault can be redundant. Redundancy is also possible, when a set of K lines are cut and M<K lines connect such that the output response function does not change. A combinational circuit in which all the faults are detectable is said to be irredundant circuit.

13. Triple Modular Redundancy(TMR) It is a fault tolerant design. Input is given to all the three systems and their outputs are given to the majority voter circuit M whose output response is the primary output. If any one of the three systems is faulty, the other two systems can mask it by using majority voter circuit M.

14. Need of un-wanted gates Output = ab + bc + a’c, which can be simplified to ab+a’c, which implies gate Y can be removed. If gate Y is removed, there will be a hazard when the input changes from 111 to 011, for an instance 0-pulse will appear. Note: The fault n stuck-at-0 is undetectable.