1. Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/04/05

2. Page 2EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (II)

3. Page 3EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Single Stuck-Fault Model 1.Single Stuck Fault (SSF) model is also referred to as the classical or standard fault model. 2.Most physical defects can be mapped into SSFs. 3.Still popularly used in industry. 4.The fault universe of a circuits with G gates is about 2Gf, where f is the average fanout count.

4. Page 4EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Local Structure Analysis 1.Simplified faulty circuit of circuit N with fault f, S(N f ), is defined as the remaining circuit by removing the stuck lines with a constant values. 2.f and g are structural equivalent  S(N f )=S(N g )  Functional eq. 3.Structural equivalence analysis can be done locally while global analysis required for functional equivalence. x y z w x y z w y z w

5. Page 5EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Local Structure Analysis 1.When fanout n of a gate is more than 1, the output wire is called a stem with n branches. x y z branch stem Reconvergent Reconvergent fanout 2.Fanout-free region B A C D E F G H I J K L Hi Hj

6. Page 6EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Fanout-free Combinational Circuits 1.In a fanout-free combinational circuit C, any test set that detects all SSFs on the PIs of C detects all SSFs in C. z 2.In a combinational circuit C, any test set that detect all SSFs on the PIs & the fanout branches of C detects all SSFs in C. The Primary Inputs (PIs) and the Fanout Branches (FBs) are called checkpoints (CPs). 3.The dominance fault collapsing reduces the number of faults dealt with from 2w to 2(I+  b i ) (where w, I, b i are counts of wires, PIs and branches of the ith fanout).

7. Page 7EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example 1.C17 in ISCAS85 benchmark: L E J B A C D HiHi HjHj F H I G K GiGi GjGj CiCi CjCj 123450 Levelization w=18, I=5, b 1 =2, b 2 =2, b 3 =2 E J B A C D HiHi HjHj F H I G K GiGi GjGj CiCi CjCj Checkpoints:

8. Page 8EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Homework 3 1.List all SSFs of C17 in ISCAS85 benchmark. E.g., A0 means the stuck-at-0 fault at wire A. 2.Collapse faults by following >dominated_falult, and =equivalent_fault, and circle the kept faults. 3.List all checkpoints and the associated faults. 4.Do the deductive fault simulation for t=(10110) considering only the faults at checkpoints. 5.Find FC and TE based on the total faults before collapsing. E J B A C D HiHi HjHj F H I G K GiGi GjGj CiCi CjCj

9. Page 9EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (I)

10. Page 10EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Applications 1.Evaluate (grade) a test (set) T. 2.Fault Dropping for Test Generation. 3.Construct fault dictionaries before testing for test compaction 4.Construct fault dictionaries for Post-test Diagnosis. 5.Analyze the operation of a circuit in the presence of the faults.

11. Page 11EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Defect Coverage Experience has shown that a test with high Fault Converage (FC) for SSFs also achieve a high DC. Defect Level (DL) is defined as the probability of shipping a defective product.

12. Page 12EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Defect Coverage Yield (Y) is defined as the probability that a manufactured circuit is defect-free. One model gives DL=1-Y 1-d.

13. Page 13EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example 1.Consider all SSFs before collapsing, assume there are 10000 faults and 2000 faults are redundant. Test set T1 can detect 8000 non-redundant faults while T2 can detect only 7200 non-redundant faults. Find their fault coverage (FC) and test efficiency (TE, test coverage for some tools)? Ans. FC(T1)=8000/10000= 80% FC(T2)=7200/10000= 72% TE(T1)= 8000/ 8000=100% TE(T2)= 7200/ 8000= 90%

14. Page 14EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Fault Dropping by Fault Simulation Fault Selection Test Generation Fault Simulation Fault Dropping TE enough? Done No

15. Page 15EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Classification of Fault Simulations 1.Serial Simulate one fault at a time. 2.Parallel Simulate W (>1) faults at a time. 3.Deductive Simulate the good circuit and deduces the behavior of all faulty circuits. 4.Concurrent Simulate only elements that are different from the corresponding ones.

16. Page 16EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Serial Fault Simulations 1.Simplest and able to handle of any type of faults. Combinational Network N Faulty Network N f with a fault f

17. Page 17EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Tasks of Fault Simulations 1.Fault Specification Fault modeling and definition Fault collapsing 2.Fault Insertion Fault selection and creation in internal data structure 3.Fault Propagation Occupy most work to propagate the effects. 4.Fault Detection & Discarding Voltage or current signal; analog allowance or digital values. A fault detect k times should be discarded, usually k=1.

18. Page 18EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Parallel Simulation 1.Parallel-Fault Fault Simulation: A good circuit and W independent faulty circuits are simultaneously simulated for ┌ (F+1)/W┐ passes. 2.Parallel-Pattern Simulation: E.g., a 32-bit integer is early used for one bit in serial simulation and 32 bits in PPFP. 3.PPSFP for SSFs. 11101011011111110001111101110101 i =0 or 1 3.2 bits required for 3-value or 4-value logic, say {0, 1, u} and {0, 1, D, D’}. (where D=good1/faulty0=↓=s-a-0) 4.Parallel-Pattern Fault Simulation: E.g., a 32-bit integer is early used for one bit in serial simulation and 32 bits in PPFP.

19. Page 19EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Deductive Fault Simulation 1.Fault List at wire i: the set of all faults that cause the values of I in N and N f to be different at the current simulated time. 2.Memory for a G-wire circuit with F faults: G(F+1) ~ O(G 2 ). 3. For a gate Z with controlling value c and inversion i: 4.A simple example of Fault-List Propagation: F C A B E 1 1 A0 B0 A0, B0, E0 0 C1 1 A0, B0, E0, F0 1 L E =L A U L B U {E0}L F ={L E - L C } U {F0}

20. Page 20EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Concurrent Fault Simulation 1.Similar to Deductive Fault Simulation but it maintains larger fault list for convenience of executing a Fault-List Event Driven Simulation. 2.A concurrent simulator processes only the active faulty circuits. 3.The main disadvantage of concurrent simulation is that it requires more memory than the other methods.