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4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION.

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Presentation on theme: "4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION."— Presentation transcript:

1 4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION

2 4/20/2006ELEC7250: Alexander 2 PROBLEM STATEMENT To write a logic simulator to verify combinational circuits given a set of input vectors and the expected output responses. To introduce a design error in the circuit and list the failing vectors and primary outputs where the errors are observed. To diagnose the design error.

3 4/20/2006ELEC7250: Alexander 3 Logic Simulation. Each PI, PO and gate were represented as a structure ( node). PI’s, PO’s contained information like name, input vector values, expected response respectively. Gate nodes also contained the fan-in list, fan-out list etc. Simple search method was used to find out the fan- out connections to their respective gates.

4 4/20/2006ELEC7250: Alexander 4 START Read input, output and gate data from simulation file into the structures. Initialize gate fan-in’s and fan- out’s to unknown X. Create structures for the inputs, outputs and gates. Read the input vector and expected response from the stimuli file into input/output nodes Feed the input vector to their respective gate inputs. Simulate the gate fan-out output and propagate to primary outputs. Is any PO = ‘X’ ? Are all PO’s =expected response? Diagnose fault and list failing vector and PO Are all test vectors simulate d ? TERMINATE YES NO YE S NO YES

5 4/20/2006ELEC7250: Alexander 5 Complexity If net list is levelized, the complexity will be proportional to the number of gates. Actual search complexity = N*N where N is number of gates. Worst case scenario = depth of circuit * N*N.

6 4/20/2006ELEC7250: Alexander 6 Back Trace Back trace - Possible error paths were listed by back tracing from PO’s, comparing the expected response with actual simulated response. Since there could be a number of paths to a given erroneous PO, many good paths maybe considered erroneous by the simulator. The actual error path is found to be detected the most number times by the test vectors.

7 4/20/2006ELEC7250: Alexander 7 Fault Dictionary Using fault dictionary – Possible faults were listed for the given circuit along with test vectors that failed for that fault. A failing test vector may give more than one possible fault. In such a case, the error path from back tracing can be used to pin point the actual fault. For larger circuits, with larger fault dictionaries, a combination of back trace and fault dictionary can give better diagnosis resolution.

8 4/20/2006ELEC7250: Alexander 8 Results for a 4 bit Ripple Carry Adder

9 4/20/2006ELEC7250: Alexander 9 Results for ISCAS’85 circuits (simulated for 1000 random vectors)

10 4/20/2006ELEC7250: Alexander 10 Conclusion and Improvements. Better search algorithms can give a simulation complexity of N where N is the number of gates. Fault dictionary and back trace are useful methods for better diagnosis resolution. Improvement – Redundant gate simulation can be removed to increase the speed. Increase the number of faults in fault dictionary and to test for larger circuits.

11 4/20/2006ELEC7250: Alexander 11 THANK YOU.


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