1. Technical University Tallinn, ESTONIA Overview: Testability Evaluation Outline Quality Policy of Electronic Design Tradeoffs of Design for Testability Testability measures Heuristic measures Probabilistic measures Calculation of testability Parker - Mc Cluskey method Cutting method Conditional probabilities based method

2. © Raimund Ubar Quality Policy Yield 2 For example 60%, other chips are faulty Testimine Defect level means: How many chips from hundred escape? Chips from manufactory

3. Technical University Tallinn, ESTONIA Introduction: The Problem is Money? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams Test coverage function Time

4. Technical University Tallinn, ESTONIA Design for Testability The problem is - QUALITY: Quality policy Yield (Y) P,n Defect level (DL) P a Design for testability Testing P - probability of a defect n - number of defects P a - probability of accepting a bad product - probability of producing a good product

5. Technical University Tallinn, ESTONIA Design for Testability The problem is - QUALITY: Quality policy Yield (Y) P,n Defect level (DL) P a n - number of defects m - number of faults tested P - probability of a defect P a - probability of accepting a bad product T - test coverage

6. Technical University Tallinn, ESTONIA Design for Testability The problem is - Money: Y(%) T(%) 10 50 90 5090 851 45255 81459 Goal: DL   T   Testability  Paradox: Testability   DL  (Y  ) DL T(%) YY 1000 1

7. Technical University Tallinn, ESTONIA Design for Testability Tradeoffs: DFT: Resynthesis or adding extra hardware Performance  Logic complexity  Area  Number of I/O  Power consumption  Yield  Economic tradeoff: C (Design + Test) < C (Design) + C (Test) Goal: DL   T   Testability  Paradox: Testability   DL  (Y  )

8. Technical University Tallinn, ESTONIA Design for Testability Economic tradeoff: C (Design + Test) < C (Design) + C (Test) C (DFT) + C (Test’) < C (Design) + C (Test) C (DFT) = ( C D + Δ C D ) + Q ( C P + Δ C P ) Design Product Test generation Testing Troubleshooting Volume C (Test) = C TGEN + (C APLIC + (1 - Y) C TS ) Q

9. Technical University Tallinn, ESTONIA Testability Criteria Qualitative criteria for Design for testability: Testing cost: –Test generation time –Test application time –Fault coverage –Test storage cost (test length) –Availability of Automatic Test Equipment The cost of re-design for testability: –Performance degradation –Area overhead –I/O pin demand

10. Technical University Tallinn, ESTONIA Testability of Design Types General important relationships:  T (Sequential logic) < T (Combinational logic) Solutions: Scan-Path design strategy  T (Control logic) < T (Data path) Solutions: Data-Flow design, Scan-Path design strategies  T (Random logic) < T (Structured logic) Solutions: Bus-oriented design, Core-oriented design  T (Asynchronous design) < T (Synchronous design)

11. Technical University Tallinn, ESTONIA Testability of Design Types T (Sequential logic) < T (Combinational logic Combinationa l circuit IN OUT R q q’ Combination al circuit IN OUT R Scan-IN Scan-OUT q q’ Solution: Scan-Path design strategy

12. Technical University Tallinn, ESTONIA Testability of Design Types T (Control logic) < T (Data path) Solutions: Scan-Path design strategie Data-Flow design

13. © Raimund Ubar 13 How to test million transistors? Scan-Path Based Testing Multi Site Test ATE H.-J.Wunderlich, U Stuttgart All memory components are made “transparent” via shift registers Test patterns Response Test System Fault

14. Technical University Tallinn, ESTONIA Testability of Design Types T (Random logic) < T (Structured logic) Solutions: Bus-oriented design, Core-oriented design System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates Random logic, structure is hidden

15. Technical University Tallinn, ESTONIA Testability Estimation Rules of Thumb Circuits less controllable Decoders Circuits with feedback Counters Clock generators Oscillators Self-timing circuits Self-resetting circuits Circuits less observable Circuits with feedback Embedded –RAMs –ROMs –PLAs Error-checking circuits Circuits with redundant nodes

16. Technical University Tallinn, ESTONIA Bad Testability: Fault Redundancy 1 & & & 1 & x1x1 x2x2 & x4x4 x3x3 y Faults at x 2 is not testable Optimized function: Internal signal dependencies: 1 & & 1 1 1 1 1 Impossible pattern, OR  XOR is not testable Redundant gates (bad design):

17. CREDES Summer School © Raimund Ubar Fault Redundancy 1 & & & 1 1 0101 1010 0101 1 Hazard control circuit: Redundant AND-gate Fault  0 is not testable 1  0 0 Error control circuitry : Decoder   1 1 E = 1 if decoder is fault-free Fault  1 is not testable E=1 17 101 Hazard

18. Technical University Tallinn, ESTONIA Hard to Test Faults Evaluation of testability:  Controllability  C 0 (i)  C 1 (j)  Observability  O Y (k)  O Z (k)  Testability 1 2 20 & & 1 2 1 x Defect Probability of detecting 1/2 60 1 2 20 & 1 2 1 i k j Y Z Controllability for 1 needed

19. © Raimund Ubar Consequeces of Bad Testability Redundant faults don’t need to be tested, because the functionality of the circuit remains correct. However, if you don’t know that the not-covered fault is redundant, the lower fault coverage will mean ambiguiety Hard-to-test faults have the same impact for random testing In deterministic testing the problem can be solved at higher cost 19

20. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability calculation: AND gate Measure: minimum number of nodes that must be set to produce 0 For inputs: C 0 (x) = C 1 (x) = 1 For other signals: recursive calculation starting from inputs C 0 (x i ) = 23 C 0 (x j ) = 11  C 0 (x k ) = C 0 (x 1 ) = 1 C 0 (x 2 ) = 1 min [C 0 (x i ), C 0 (x j ) ] + 1 = = min (23,11) + 1 = 12

21. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability calculation: Measure: minimum number of nodes that must be set to produce 1 For inputs: C 0 (x) = C 1 (x) = 1 For other signals: recursive calculation starting from inputs C 1 (x i ) = 23 C 1 (x j ) = 11 & C 1 (x k ) = C 1 (x i ) + C 1 (x j ) + 1 = = 23 + 11 + 1 = 35 C 1 (x 1 ) = 1 C 1 (x 2 ) = 1

22. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability calculation: OR gate Measure: minimum number of nodes that must be set to produce 0 For inputs: C 0 (x) = C 1 (x) = 1 For other signals: recursive calculation starting from inputs C 0 (x i ) = 23 C 0 (x j ) = 11 1 C 0 (x k ) = C 0 (x 1 ) = 1 C 0 (x 2 ) = 1 C 0 (x i ) + C 0 (x j ) + 1 = = 23 + 11 + 1 = 35

23. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability calculation: EXOR gate Measure: minimum number of nodes that must be set in order to produce 0 For inputs: C 0 (x) = C 1 (x) = 1 For other signals: recursive calculation starting from inputs C 0 (x i ) = 23 C 1 (x i ) = 18  C 0 (x k ) = min { [ C 0 (x i ) + C 0 (x j ) ], [C 1 (x i ) + C 1 (x j ) ] } + 1 = min{ (23 +12), (18 + 20) } + 1 = min (35,38) + 1 = 36 C 0 (x 1 ) = 1 C 0 (x 2 ) = 1 C 0 (x j ) = 12 C 1 (x j ) = 20

24. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability calculation: Measure: minimum number of nodes that must be set in order to produce 0 or 1 For inputs: C 0 (x) = C 1 (x) = 1 For other signals: recursive calculation rules: & xy & x1x1 y x2x2 1 x1x1 y x2x2  x1x1 y x2x2 C 0 (y) = min  C 0 (x 1 ), C 0 (x 2 )  + 1 C 1 (y) = C 1 (x 1 ) + C 1 (x 2 ) + 1 C 0 (y) = C 1 (x) + 1 C 1 (y) = C 0 (x) + 1 C 1 (y) = min  C 1 (x 1 ), C 1 (x 2 )  + 1 C 0 (y) = C 0 (x 1 ) + C 0 (x 2 ) + 1 C 0 (y) = min  (C 0 (x 1 ) + C 0 (x 2 )), (C 1 (x 1 ) + C 1 (x 2 ))  + 1 C 1 (y) = min  (C 0 (x 1 ) + C 1 (x 2 )), (C 1 (x 1 ) + C 0 (x 2 ))  + 1

25. Technical University Tallinn, ESTONIA Heuristic Testability Measures Observability calculation: Measure: minimum number of nodes which must be set for fault propagating For outputs: O(y) = 1 For other signals: recursive calculation starting from inputs O(x i ) = O(x k ) + C 1 (x j ) = = 23 + 11 + 1 = 35 C 1 (x j ) = 11  O(y) = 1 O(x k ) = 23

26. Technical University Tallinn, ESTONIA Heuristic Testability Measures Observability calculation: Measure: minimum number of nodes which must be set for fault propagating For outputs: O(y) = 1 For other signals: recursive calculation rules: & xy & x1x1 y x2x2 1 x1x1 y x2x2  x1x1 y x2x2 O(x 1 ) = O(y) + C 1 (x 2 ) + 1 O(x) = O(y) + 1 O(x 1 ) = O(y) + C 0 (x 2 ) + 1 O(x 1 ) = O(y) + 1

27. Technical University Tallinn, ESTONIA Heuristic Testability Measures Testability calculation: Measure: sum of controllability and observability O(x i ) = 35 C 1 (x j ) = 11  O(y) = 1 O(x k ) = 23 T(x  0) = C 1 (x) + O(x) T(x  1) = C 0 (x) + O(x) T(x i = 0) = O(x i ) + C 1 (x j ) = 35 + 16 = 51 C 1 (x i ) = 16

28. Technical University Tallinn, ESTONIA Heuristic Testability Measures Controllability and observability: & && && & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro

29. Technical University Tallinn, ESTONIA Heuristic Testability Measures Testability calculation: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro T(x  0) = C 1 (x) + O(x) T(x  1) = C 0 (x) + O(x)

30. Technical University Tallinn, ESTONIA Probabilistic Testability Measures Controllability calculation: Measure: probability to produce 0 or 1 at the given nodes For inputs: C 0 (i) = p(x i =0) = 1 - p xi C 1 (i) = p(x i =1) = 1 - p(x i =0) = p xi For other signals: recursive calculation rules: & xy & x1x1 y x2x2 p y = p x1 p x2 p y = 1 - p x 1 x1x1 y x2x2 p y = 1 - (1 - p x1 )(1 - p x2 ) & x1x1 y xnxn... 1 x1x1 y xnxn

31. Technical University Tallinn, ESTONIA Probabilistic Testability Measures Probabilities of reconverging fanouts:  x1x1 y x2x2 p y = 1 - (1 - p a ) (1 - p b ) = 1 - 0,75*0,75 = 0,44 & x1x1 y x2x2 & 1 a b & x y p y = p x p x = p x 2 ? Signal correlations: p y = (1 – p x1 ) p x2 + (1 – p x2 ) p x1 = 0,25 + 0,25 = 0,5

32. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities & x1x1 y x2x2 & 1 p y = 1 - (1 - p a ) (1 - p b ) = = 1 - (1 - p x1 (1 - p x2 ))(1 - p x2 (1 - p x1 )) = = 1 - (1 - p x1 + p x1 p x2 ) (1 - p x2 + p x1 p x2 ) = = 1 – (1 - p x2 + p x1 p x2 - p x1 + p x1 p x2 - p 2 x1 p x2 + + p x1 p x2 - p x1 p 2 x2 + p 2 x1 p 2 x2 ) = = 1 – (1 - p x2 + p x1 p x2 - p x1 + p x1 p x2 - p x1 p x2 + + p x1 p x2 - p x1 p x2 + p x1 p x2 ) = = p x2 - p x1 p x2 + p x1 - p x1 p x2 + p x1 p x2 - - p x1 p x2 + p x1 p x2 - p x1 p x2 ) = = p x1 + p x2 - 2p x1 p x2 = 0,5 a b Parker - McCluskey algorithm:

33. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities Straightforward methods: & & & a c y & b 1 2 3 2121 2 2323 Parker - McCluskey algorithm: p y = p c p 2 = (1- p a p b ) p 2 = = (1 – (1- p 1 p 2 ) (1- p 2 p 3 )) p 2 = = p 1 p 2 2 + p 2 2 p 3 - p 1 p 2 3 p 3 = = p 1 p 2 + p 2 p 3 - p 1 p 2 p 3 = 0,38 Calculation gate by gate: p a = 1 – p 1 p 2 = 0,75, p b = 0,75, p c = 0,4375, p y = 0,22 For all inputs: p k = 1/2

34. Technical University Tallinn, ESTONIA Probabilistic Testability Measures Parker-McCluskey: && & a c y & b 1 2 3 2121 2 2323 Observability: p(  y/  a = 1) = p b p 2 = = (1 - p 2 p 3 ) p 2 = p 2 - p 2 2 p 3 = p 2 - p 2 p 3 = 0,25 x Testability: p(a  1) = p(  y/  a = 1) (1 - p a ) = = (p 2 - p 2 p 3 )(p 1 p 2 ) = = p 1 p 2 2 - p 1 p 2 2 p 3 = = p 1 p 2 - p 1 p 2 p 3 = 0,125 For all inputs: p k = 1/2

35. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities Idea: Complexity of exact calculation is reduced by using lower and higher bounds of probabilities Technique: Reconvergent fan-outs are cut except of one Probability range of [0,1] is assigned to all the cut lines The bounds are propagated by straightforward calculation Cutting method & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Lower and higher bounds for the probabilities of the cut lines: p 71 := (0;1), p 72 := (0;1), p 73 := 0,75

36. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities For all inputs: p k = 0,5 Reconvergent fan-outs are cut except of one – 7 1 and 7 2 Probability range of [0,1] is assigned to all the cut lines - 7 1 and 7 2 The bounds are propagated by straightforward calculation Cutting method & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Calculation steps: 1/2 [0,1] [1/2,1] 3/4 1/2 5/8 [1/2,1] [1/2,3/4] [1/4,3/4] [34/64,54/64] Exact value: 41/64

37. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities Method of conditional probabilities y x P(y) = p(y/x=0) p(x=0) + p(y/x=1) p(x=1) Probabilitiy for – y Conditions – x  set of conditions Conditional probabilitiy Idea of the method: Two conditional probabilities are calculated along the paths (NB! not bounds as in the case of the cutting method) Since no reconvergent fanouts are on the paths, no danger for signal correlations

38. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities Method of conditional probabilities & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y y x NB! Probabilities P k = [P k * = p(x k /x 7 =0), P k ** = p(x k /x 7 =1)] are propagated, not bounds as in the cutting method. For all inputs: p k = 1/2 3/4 [1,1/2] [1/2,3/4] [1/2,5/8] [1/2,11/16] p y = p(y/x 7 =0)(1 - p 7 ) + p(y/x 7 =1)p 7 = (1/2 x 1/4) + (11/16 x 3/4) = 41/64 1/2

39. Research in ATI © Raimund Ubar BDDs and Testing of Logic Circuits By the BDD for F(X) we can generate test patterns only for testing inputs 39 How about testing the internal nodes of the circuit?  SSBDD The tasks on BDDs: (1)Pattern simulation (analysis) (2)Pattern generation (synthesis)

40. Technical University Tallinn, ESTONIA 40 Test Generation with SSBDDs Test generation for: x 21  0 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 1010 1 0 0 0 0 1010 1010 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1 1010 x 1 x 2 x 3 x 4 y 1 1 0 - Test pattern: 1  0

41. Technical University Tallinn, ESTONIA Calculation of Signal Probabilities p y = p(L 1 ) + p(L 2 ) = = p 1 p 21 p 23 + (1 - p 1 ) p 22 p 3 p 23 = = p 1 p 2 + (1 - p 1 )p 2 p 3 = 0,38 & & & a c y & b 1 2 3 2121 2 2323 For all inputs: p k = 1/2 Using BDDs: 2121 2323 3 y L1L1 L2L2 p 1 p 21 p 23 (1-p 1 )p 22 p 3 p 23 1 2 #1#1 #0 1 3 2 y p2 p1p2 p1 p 2 (1-p 1 )p 3 #1#1 #0

42. Technical University Tallinn, ESTONIA Probabilistic Testability Measures Using BDDs: 1 2121 2 2323 3 y L1L1 L2L2 Observability: p(  y/  x 21 = 1) = p(L 1 ) p(L 2 ) p(L 3 ) = = p 1 p 23 p 22 (1 - p 3 ) = 0,125 & & & a c y & b 1 2 3 2121 2 2323 x L3L3 Testability: p(x 21  0) = p 21 p(  y/  x 21 = 1) = = p 21 p(L 1 ) p(L 2 ) p(L 3 ) = = p 2 p 1 (1 - p 3 ) = 0,125 Fault

43. Technical University Tallinn, ESTONIA Probabilistic Testability Measures Using BDDs: Observability: p(  y/  x 2 = 1) = p(L 1 ) p(L 2 ) = p(L 2 )= = p 1 = 0,5 & & & a c y & b 1 2 3 2121 2 2323 x Fault 1 3 2 y p 1 (1-p 2 ) #1#1 #0 L2L2 L1L1 Testability: p(x 21  0) = p 2 p(  y/  x 21 = 1) = = p 2 p 1 = 0,25

44. Technical University Tallinn, ESTONIA Heuristic and Probabilistic Measures p y =   p x k: L k  L(1) x  X k CC 1 [y] = min {  CC 1 (x(m) } + const. k: l k  L(1) m  M k Heuristic controllability measure: Probabilistic measure:

45. Technical University Tallinn, ESTONIA Heuristic Controllabilities Using BDDs for controllability calculation: & & & a c y & b 1 2 3 2121 2 2323 Gate level calculation 1 2121 2 2323 3 y L1L1 L2L2 331 33 BDD-based algorithm for the heuristic measure is the same as for the probabilistic measure C 1 (y) = min [(C 1 (L 1 ), C 1 (L 2 )] + 1 = = min [C 1 (x 1 ) + C 1 (x 2 ), C 0 (x 1 ) + C 1 (x 2 ) + C 1 (x 3 )] + 1 = = min [2, 3] + 1 = 3

46. Technical University Tallinn, ESTONIA Calculating Probabilities on BDDs p y =   p x L k  L(1) x  X k Example: L 1 = (1,2 1,2 3 ) L 2 = (1,2 2,3,2 3 ) p y = p 1 p 2 + (1-p 1 )p 2 p 3 = 0,375 2121 2323 3 y L1L1 L2L2 p 1 p 21 p 23 (1-p 1 )p 22 p 3 p 23 1 2 #1#1 #0 Set of nodes on the path Set of paths

47. Technical University Tallinn, ESTONIA Register Transfer Level and DDs Word-level Decision Diagrams:

48. Research in ATI © Raimund Ubar The basic idea: Topological View on Fault Propagation on BDDs 48 m y 1 0 lmlm l1l1 l0l0 GyGy

49. Research in ATI © Raimund Ubar Generalization of BDDs m y 1 0 lmlm l1l1 l0l0 GyGy m Y 1 0 2 h FkFk FnFn l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GYGY Binary DD 2 terminal nodes and 2 edges from each node General case of DD n  2 terminal nodes and n  2 edges from each node Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels 49

50. Technical University Tallinn, ESTONIA Calculating Observabilities RT-Level Circuits p y =   p x L k  L(1) x  X k Gate-level calculation: RT-level calculation: P(y=z(m T )) =   P(x=e) L i  L(m 0,m T ) x  X i m Y 1 0 2 FkFk FnFn l0l0 l1l1 l2l2 lmTlmT lklk l k+1 F k+1 lnln lmlm GYGY DD for a Data Path: m0m0 mTmT

51. Technical University Tallinn, ESTONIA Calculating Observabilities RT-Level Data Paths p y =   p x L k  L(1) x  X k Gate-level calculation: Example: P(R 2 = R 1  R 2 ) = P(y 4 =2) P(y 3 =3) P(y 2 =0) RT-level calculation: P(y=z(m T )) =   P(x=e) L i  L(m 0,m T ) x  X i

52. Technical University Tallinn, ESTONIA Calculating Probabilities for FSM p y = p(y=1) =   p x L k  L(1) x  X k 3,4 0 2 q 1 0 1 0 q  1  4 x A  2 1  5 x B  3 Gate-level calculation: RT-level calculation: P(y=k) =   P(x=e) L i  L(k) x  X i Example: P(q=5) = P(q=2)P(x B =0) + P(q=3) + P(q=4) Nonterminal nodes (control-path):