1. Technical University Tallinn, ESTONIA Test generation Gate-level methods  Functional testing: universal test sets  Structural test generation  Path activation conception  Algorithms: D, Podem, Fan  Test generation for multiple faults  Test generation for sequential circuits  Random test generation  Genetic algorithms for test generation High-level and hierarchical methods  Test generation for digital systems  Test generation for microprocessors

2. Technical University Tallinn, ESTONIA Test generation Universal test sets 1. Exhaustive test (trivial test) 2. Pseudo-exhaustive test Properties of exhaustive tests 1. Advantages (concerning the stuck at fault model): - test pattern generation is not needed - fault simulation is not needed - no need for a fault model - redundancy problem is eliminated - single and multiple stuck-at fault coverage is 100% - easily generated on-line by hardware 2. Shortcomings: - long test length (2 n patterns are needed, n - is the number of inputs) - CMOS stuck-open fault problem

3. Technical University Tallinn, ESTONIA Test generation Pseudo-exhaustive test sets: –Output function verification maximal parallel testability partial parallel testability –Segment function verification Output function verification 4 4 4 4 2 16 = 65536 >> 4x16 = 64 > 16 Exhaustive test Pseudo- exhaustive sequential Segment function verification F & 1111 0101 0011 Pseudo- exhaustive parallel

4. Technical University Tallinn, ESTONIA Functional testing: universal test sets Output function verification (maximum parallelity) Exhaustive test generation for n-bit adder: Good news: Bit number n - arbitrary Test length - always 8 (!) 0-bit testing 2-bit testing 1-bit testing 3-bit testing … etc Bad news: The method is correct only for ripple-carry adder

5. Technical University Tallinn, ESTONIA Testing carry-lookahead adder General expressions: n-bit carry-lookahead adder:

6. Technical University Tallinn, ESTONIA Testing carry-lookahead adder 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 For 3-bit carry lookahead adder for testing only this part of the circuit at least 9 test patterns are needed (i.e. pseudoexhaustive testing will not work) Increase in the speed implies worse testability Testing  0 Testing  1 R

7. Technical University Tallinn, ESTONIA Test generation Output function verification (partial parallelity) x1x1 x2x2 x3x3 x4x4 F 1 (x 1, x 2 ) F 2 (x 1, x 3 ) F 3 (x 2, x 3 ) F 4 (x 2, x 4 ) F 5 (x 1, x 4 ) F 6 (x 3, x 4 ) 0011- - 010101 010110 00-11- 000111 0011- 0 F1F1 F3F3 F2F2 F4F4 F5F5 Exhaustive testing - 16 Pseudo-exhaustive, full parallel - 4 Pseudo-exhaustive, partially parallel - 6

8. Technical University Tallinn, ESTONIA Structural Test Generation A fault a/0 is sensitisized by the value 1 on a line a A test t = 1101 is simulated, both without and with the fault a/0 The fault is detected since the output values in the two cases are different A path from the faulty line a is sensitized (bold lines) to the primary output Structural gate-level testing: fault sensitization:

9. Technical University Tallinn, ESTONIA Structural Test Generation Structural gate-level testing: Path activation & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault sensitisation: x 7,1 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: x 7 = D = 0: x 3 = 1, x 4 = 1 b = 1: (already justified) c = 1: (already justified) Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present 1 1 1 1 Test pattern

10. Technical University Tallinn, ESTONIA Test generation Test generation for a bridging fault: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7,1 =  D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: b = 1: x 5 = 0 y Component F(x 1,x 2,…,x n ) Defect WdWd Activate a path Bridge between leads 7 3 and 6 WdWd

11. Technical University Tallinn, ESTONIA Test generation Multiple path fault propagation: 111 1 11 1 1 x1x1 x2x2 x3x3 x4x4 y D D D 0 0 111 1 11 1 1 x1x1 x2x2 x3x3 x4x4 y D D D 0 0 D D 1 0 0 Single path activation is not possible Three paths simultaneously activated DD

12. Technical University Tallinn, ESTONIA Test generation D - algorithm (Roth, 1966): Select a fault site, assign D Propagate D along all available paths using D-cubes of gates Backtracking, to find the inputs needed  1 2 3 4 D 1 1 D Example:  1 2 3 4 D 1 D 1 Fault site Propagation D-cubes for AND-gate

13. Technical University Tallinn, ESTONIA Test generation D - algorithm: Singular cover for C = NAND (A,B): a b c 1 1 0 x 0 1 0 x 1 Propagation D-cubes for C = NAND (A,B): a b c 1 D D D 1 D D D D Intersection of cubes: Let have 2 D-cubes A = (a 1, a 2,... a n ) B = (b 1, b 2,... b n ) where a i, b j   0,1,x,D,D) 1) x  a i = a i 2) If a i  x and b i  x then a i  b i = a i if b i = a i or a i  b i =  otherwise 3) A  B =  if for any i: a i  b i =  Primitive D-cubes for NAND and c  0: a b c 0 x D x 0 D & & & 1 3 2 5 4 6 Propagation of D-cubes in the circuit: 1 2 3 4 5 6 D-drive: Primitive cube for x 2  1 D Propagate D through G4 1 D D Propagate D through G6 1 D D 1 D Consistency operation: Intersect with G5 1 D 0 D 1 D

14. Technical University Tallinn, ESTONIA Test generation Multiple path fault propagation by DDs: 1 11 1 1 1 1 1 x1x1 x2x2 x3x3 x4x4 y D D D 0 0 D D 1 0 0 x 21 x 11 x 31 x 12 x 22 x 32 x 41 x 23 x 33 x3x3 x 24 x 42 y Functional DD Structural DD x2x2 x1x1 y x3x3 x4x4 x1x1 x4x4 x3x3

15. Technical University Tallinn, ESTONIA Test generation PODEM - algorithm (Goel, 1981): 1. Controllability measures are used during backtracking Decision gate: The “easiest” input will be chosen at first Imply gate: The “most difficult” input will be chosen at first 2. Backtracking ends always only at inputs 3. D-propagation on the basis of observability measures & 0 & 1 0 1

16. Technical University Tallinn, ESTONIA Test generation FAN - algorithm (Fujiwara, 1983): 1. Special handling of fan-outs (by using counters) PODEM: backtracking continues over fan-outs up to inputs FAN: backtracking breaks off, the value is chosen on the basis of values in counters 2. Heuristics is introduced into D-propagation PODEM: moves step by step (without predicting problems) FAN: finds bottlenecks and makes appropriate decisions at the beginning, before starting D-propagation 1 (C = 6) 0 (C = 3) 0 (C = 2) 1 Chosen value:

17. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 1 0 - 1 Testing Stuck-at-0 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 12  0, x 21  0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0

18. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 1 1 1 Test pattern: 1 0 Tested faults: x 12  0, x 31  0, x 4  0 Testing Stuck-at-0 faults on paths:

19. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 0 1 1 0 1 Test pattern: 1 0 Tested faults: x 22  0, x 32  0 Not tested: x 13  1 Testing Stuck-at-0 faults on paths:

20. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 0 0 1 1 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 12  1, x 22  1 Not tested: x 11  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1

21. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 0 1 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 21  1, x 31  1, x 13  0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1

22. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 1 0 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested fault: x 4  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1 Not yet tested fault: x 32  1

23. Technical University Tallinn, ESTONIA Transformation of BDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x4x4 x3x3 x2x2 SSBDD: Optimized BDD: x1x1 y x2x2 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x12x12 x3x3 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x4x4 x3x3 x2x2 x3x3 BDD:

24. Technical University Tallinn, ESTONIA Example: Test Generation with BDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y D 1 0 - D Testing Stuck-at faults on inputs: Test pair D=0,1: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 1  0, x 1  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 x1x1 y x2x2 x4x4 x3x3 x2x2 SSBDD: BDD:

25. Technical University Tallinn, ESTONIA Test generation Test generation by using disjunctive normal forms

26. Technical University Tallinn, ESTONIA Multiple Fault Testing Multiple faults fenomena: Multiple stuck-fault (MSF) model is a straightforward extension of the single stuck-fault (SSF) model where several lines can be simultaneously stuck If n - is the number of possible SSF sites, there are 2n possible SSFs, but there are 3 n -1 possible MSFs If we assume that the multiplicity of faults is no greater than k, then the number of possible MSFs is  k i=1 {C n i }2 i The number of multiple faults is very big. However, their consideration is needed because of possible fault masking

27. Technical University Tallinn, ESTONIA Multiple Fault Testing Fault masking Let T g be a test that detects a fault g A fault f functionally masks the fault g iff the multiple fault { f, g } is not detected by any pattern in T g The test 011 is the only test that detects the fault c  0 The same test does not detect the multiple fault { c  0, a  1} Thus a  1 masks c  0 Let T g ’  T be the set of all tests in T that detect a fault g A fault f masks the fault g under a test T iff the multiple fault { f, g } is not detected by any test in T g ’ Example: Fault a  1 Fault c  0

28. Technical University Tallinn, ESTONIA Multiple Fault Testing Circular fault masking Example: The test T = {1111, 0111, 1110, 1001, 1010, 0101} detects every SSF The only test in T that detects the single faults b  1 and c  1 is 1001 However, the multiple fault { b  1, c  1} is not detected because under the test vector 1001, b  1 masks c  1, and c  1 masks b  1  &  & 1/0  1 1 0/1 1/0 1 1 0 0/1 a b c d Multiple fault F may be not detected by a complete test T for single faults because of circular masking among the faults in F

29. Technical University Tallinn, ESTONIA Multiple Fault Testing To test a path under condition of multiple faults, two pattern test is needed As the result, either the faults on the path under test are detected or the masking fault is detected Example: The lower path from b to output is under test A pair of patterns is applied on b There is a masking fault c  1 1st pattern: fault on b is masked 2nd pattern: fault on c is detected  &  & 10  11 11(00) 10 (11) 11 01 (00) 01 00 a b c d Testing multiple faults by pairs of patterns The possible results: 01 - No faults detected 00 - Either b  0 or c  1 detected 11 - The fault b  1 is detected  1 faults (11)

30. Technical University Tallinn, ESTONIA Test generation Testing multiple faults by groups of patterns Multiple fault: x 1  1, x 2  0, x 3  1 x31x31 x20x20 x11x11 T1 T2T3 Fault masking Fault detecting An example where the method of test pairs does not help

31. Technical University Tallinn, ESTONIA Test generation Method of pattern groups on DDs x1x1 y x2x2 x1x1 x3x3 x4x4 x1x1 x2x2 x3x3 & & & 1 & x1x1 x2x2 x3x3 x4x4 y Disjunctive normal forms are trending to explode DDs provide an alternative Test group for testing a part of circuit: x 1 x 2 x 3 x 4 y 1 1 0 - 1 0 1 0 - 0 1 0 0 - 0 -

32. Technical University Tallinn, ESTONIA Test generation Test generation for sequential circuits Time frame model: CC R RRR x x x x yy y y Fault sensitization: Test pattern consists of an input pattern and a state Fault propagation: To propagate a fault to the output, an input pattern and a state is needed Line justification: To reach the needed state, an input sequence is needed

33. Technical University Tallinn, ESTONIA Hierarchical Test Generation In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes These modes will usually contain: –a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or –a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) In the hierarchical approach, top-down and bottom-up strategies can be distinguished

34. Technical University Tallinn, ESTONIA Hierarchical Test Generation Approaches A B C D a D c A = ax D: B = bx C = cx A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a,c,D fixed x - free a’ c’ a Bottom-up approach:Top-down approach: a’,c’,D’ fixed x - free System Module c

35. Technical University Tallinn, ESTONIA Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c A = ax D: B = bx C = cx a,c,D fixed x - free a System Module c

36. Technical University Tallinn, ESTONIA Hierarchical Test Generation Approaches Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a’ c’ a’,c’,D’ fixed x - free System Module

37. Technical University Tallinn, ESTONIA Test Generation y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 1  IN  R 1  R 1 * R 1 Test program:

38. Technical University Tallinn, ESTONIA Test Generation y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram High-level test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = 0032 Data: For all specified pairs of (R 1, R 2 ) Test program:

39. Technical University Tallinn, ESTONIA Test Generation Transparency functions on Decision Diagrams: Y = C  y 3 = 2, R 2 ’ = 0 C - to be tested R 1 = B  y 1 = 2, R 3 ’ = 0 R 1 - to be justified High-level path activation on DDs

40. Technical University Tallinn, ESTONIA Test Generation DD synthesis for control path FSM state transitions and output functions DD for the FSM: q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4

41. Technical University Tallinn, ESTONIA Test Generation High-level DDs Data path Control path q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4

42. Technical University Tallinn, ESTONIA Test Generation for Digital Systems Test generation steps: Fault manifestation Fault-effect propagation Constraints justification y 3 =2 R’ 2 =0 y 2  0 R 3 = D= D A  R’ 1 A = D= D 1 1 = D= D 2 B = D= D 2 3 =0 y 1 =2=2 y 3  0 C = D= D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation for data-path (example):

43. Technical University Tallinn, ESTONIA Test Generation for Digital Systems Test generation step: Fault-effect propagation y 3 = 2= 2 R’ 2 = 0= 0 y 2 = 0  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 = 0= 0 y 1 = 2= 2 y 3 = 0  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 y 3  0 CR’ 2 C 2 Y,R 3 1 0 0 2 0 C+R’ 2 R’ 3 q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4

44. Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 3  0 CR’ 2 C 2 Y,R 3 0 1 0 0 2 0 y 1 R’ 1 3 B F(B,R’ 3 )  0 R 1 1 0 2 0 C+R’ 2 R’ 3 y 2 2 A 2R’ 2  0R 2 0 1 2 3 R’ 2 Path activation procedures on DDs: q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4 Test generation step: Line justification Time: t-1

45. Technical University Tallinn, ESTONIA Test Generation for Digital Systems Symbolic test sequence: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation example:

46. Technical University Tallinn, ESTONIA Test Generation I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Test program generation for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

47. Technical University Tallinn, ESTONIA Test Generation Test program generation for a microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test for adder: Instruction sequence I 5 I 1 I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

48. Technical University Tallinn, ESTONIA Test Generation Test program generation for a microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test for decoder: Instruction sequence I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

49. Technical University Tallinn, ESTONIA Test Generation Hierarchical approach with functional fault model: