1. High-Level Test Generation

2. Test Generation by Enhancing Validation Test Sets* * L. Lingappan, et al., VLSI Design, 2007 (Paper available on the class website)

3. SAT-Based Diagnosis3 Basic Idea Reuse validation test sequences Fixed control sequence, only data path values need to be determined Precomputed module tests are used If validation sequences are instruction- level, so are the generated tests RTL level analysis means faster times

4. SAT-Based Diagnosis4 Details Basis for analysis: RTL circuit and controller FSM CDFG and state transition sequence for a given validation test sequence Not all test sequences are analyzed for all precomputed test vectors because this could be computationally expensive. Instead, heuristics are used to determine compatibility.

5. SAT-Based Diagnosis5 Process Fault simulate validation test sequences and determine the activation time cycle for each detected fault. If a detected fault falls within a module, the sequence is a candidate for applying precomputed test vectors Determine compatibility of each test vector with the sequence If compatible, then justify and propagate

6. SAT-Based Diagnosis6 Example RTL Circuit

7. SAT-Based Diagnosis7 Controller Specification

8. SAT-Based Diagnosis8 CDFG and State Transition Sequence Exercised by test T1

9. SAT-Based Diagnosis9 Activation and Detection Cycle for Target Fault

10. SAT-Based Diagnosis10 Justification of Required Values-1

11. SAT-Based Diagnosis11 Justification of Required Values-2

12. SAT-Based Diagnosis12 Circuits Used in Experiments

13. SAT-Based Diagnosis13 Test Generation Results

14. Test Generation with Functional Fault Modleing* * Hansen and Hayes, VLSI Test Symposium, 1995, pp. 20-28.

15. SAT-Based Diagnosis15 Summary High-level fault modeling ensuring coverage of low-level (physical or single-stuck-line) faults. Fault effects induced from low (gate) to high (RTL or functional) level Allows discovery of minimum test sets at the high level that are hard to find by low (gate-level) techniques

16. SAT-Based Diagnosis16 Functional Fault Models General Faults (Universal) Pin Faults Both of the above are implementation and technology independent Induced faults: Physically Induced Faults (PIFs) Derived from an implementation by the induction process, hence implementation dependent and may be technology dependent. PIFs derived from single stuck-at faults are denoted as SIFs in the paper.

17. SAT-Based Diagnosis17 Faults, Functions, and Tests

18. SAT-Based Diagnosis18 Example Consider the effect of some sample SAFs on the circuit function: A SA0 A SA1 AP SA0

19. SAT-Based Diagnosis19 SIFs of the Example Circuit Consider Fault Dominance: Top 6 dominate the rest, hence only need to cover these.

20. SAT-Based Diagnosis20 Minimal SIF Test Set

21. SAT-Based Diagnosis21 Dependence on Implementation (b) and (c) have fault functions not covered by those of (a). Hence require additional SIFs

22. SAT-Based Diagnosis22 Extension to Ripple-Carry Circuit C i+1 M CiCi AiAi BiBi M C0C0 A0A0 B0B0 M C1C1 A1A1 B1B1 M C2C2 A2A2 B2B2 M C3C3 A3A3 B3B3 C4C4 How many SIF tests are required for the RCC?

23. SAT-Based Diagnosis23 Test Set Sizes

24. SAT-Based Diagnosis24 Larger Examples CLA Generator (74182) Eliminate the logic gates for G and P in the carry circuit Cascade the above module as in the RCC. How do the SIFs change for the module? How many tests for the whole circuit?

25. SAT-Based Diagnosis25 Tests Required for 4-bit CLA Generator

26. SAT-Based Diagnosis26 4-bit Adder (74283) The 10 tests for CLA can be extended to cover the XOR modules. Hence 10 tests suffice for this circuit also.

27. SAT-Based Diagnosis27 ALU Circuit (74181) CLA again dominates the test generation. 12 Tests are required, of which 10 correspond to testing CLA.

28. SAT-Based Diagnosis28 Summary of Results (For Medium Circuits)

29. SAT-Based Diagnosis29 The paper goes on to apply the technique to ISCAS85 circuits. They needed to extract high-level models for these circuits by painstaking reverse-engineering. These models are available from Prof. Hayes’ website at U. Michigan.

30. SAT-Based Diagnosis30 Conclusion Physical fault effects induced at the functional level Unlike prior high-level models, PIFs allow complete low-level coverage. However, the analysis is not automatic and the results do depend on the implementation The technique allowed obtaining provably minimum test sets for various common known implementations.