Electronic developments for the HADES RPC wall: overview and progress A. Gil a, D. Belver b, P. Cabanelas b, E. Castro b, J. Díaz a, J.A. Garzón b, D.González-Díaz c, W. Koenig c, J.S. Lange c, G. May, P. Skott c, M. Traxler c a IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain. b LabCAF, Dpto. de Física de Partículas, Universidade de Santiago de Compostela, Santiago de Compostela, 15782, Spain. c GSI, Darmstadt,64291, Germany. In this presentation I will show the new front End Electronics for the Hades Experiment Actually there are 3 groups in Spain and 1 germany at GSI involved in the project. 18 segundos TWEPP-07 3-7 September 2007 Prague

OUTLINE INTRODUCTION TO HADES EXPERIMENT OVERVIEW OF TESTED ELECTRONICS FRONT-END ELECTRONICS DAUGHTERBOARD MOTHERBOARD READ OUT SYSTEM RESULTS CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS PLAN FOR THE NEXT TESTS

OUTLINE INTRODUCTION TO HADES EXPERIMENT OVERVIEW OF TESTED ELECTRONICS FRONT-END ELECTRONICS DAUGHTERBOARD MOTHERBOARD READ OUT SYSTEM RESULTS CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS PLAN FOR THE NEXT TESTS

HADES EXPERIMENT High Acceptance DiElecton Spectrometer Located at the SIS accelerator of GSI, Darmstadt (Germany) Detection of electron-positron pairs produced in relativistic hadron-nucleus and nucleus-nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot and compressed. Consists of several subdetectors for: Tracking Triggering Particle identification Momentum reconstruction HADES is a High accepatance di electon spectrometer, (that detects electron pairs) for the detecion of electron-positron pairs produced in relativistic hadron-nucleus and nucleus –nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot compressed. Consists of several subdetectos providing tracking, triggering, particle identification and momentum reconstruction capabilities. 17 segundos TOT 63 seg GET SOMETHING FROM (OBTAINED FROM FRONT COVER OF ANUAL GSI REPORT): The front cover shows an artist's view of the High Acceptance Dielectron Spectrometer HADES installed in the target hall served by the SIS18 accelerator. The spectrometer detects rare leptonic decays of neutral vector mesons which are produced in the central reaction volume of heavy-ion collisions. The detector is capable of digitizing and filtering all relevant signals produced by reaction products at collision rates of up to 20 kHz. The detectors, which are moved apart along the beam axis in the image, are packed closely around the target for experiments to achieve polar angle coverage between 18 and 85 degrees. Six superconducting coils provide a toroidal magnetic field with a maximum bending power of 0.3 Tm. So far, the electron pair (i.e. e+ e-) production has been investigated in C+C, Ar+KCl and p+p reactions. The pair emission rate was measured over almost six orders of magnitude in the pair invariant mass range between 50 and 1000 MeV/c2 (spectrum shown in the foreground). The experimental data clearly evidences contributions to the pair yield from the early phase of the collision. Information about the properties of mesons imbedded in dense nuclear medium can be obtained by careful analysis of the spectral distribution of emitted electron pairs. Elementary reactions are exploited to scrutinize our knowledge about the various emission processes. The histogram in the background exemplarily shows the exclusive reconstruction of η-meson production in p+p reactions. HADES will continue its experimental program with p and π-induced reactions, and, after replacing the inner time-of-flight system by a novel RPC detector and upgrading the data acquisition system, with experiments addressing heavier collision systems. Goal of the Hades RPC project: upgrade the low angles Time of Flight (TOF) detector

HADES EXPERIMENT low particle rate (up to 700 Hz/cm2) Area of polar angles <45º low particle rate (up to 700 Hz/cm2) Existing temporary low angles TOF detector (called TOFino): - Low time resolution (350ps) - Low granularity RPC Beam RICH Target Upgrade using RPC technology: Time resolutions lower than 100ps Cost-effective solution MDCs Coil TOFino The picture shows the cross section of HADES, which has several detectors: RICH surrounds the target for detection of electrons and positrons Multi-Wire Drift chambers: track particles TOF: time of flight measurement and is made of plastic scintillator rods. Shower: particle multiplicity to trigger on collision centrality. The lower angle region of the TOF detector is called Tofino. This region will be replaced for the RPC wall. ---------------------------------------------------------- is a diamond detector. Is first detector wich Surrounds the target. Crucial for lepton identification. Blind to hadron. Multi-wire Drift Chambers : Are used for track reconstruction before and after the magnetic field with space resolutions below 140um. TOF wall: is made of Plastic scintillator rods and provides Multiplicity condition. High resolution timing for sepatarion of leptons from fast pions. Time resol 100-150ps. Space resol 1.5-2.3 cm. 45º<θlab<85º Shower detector: To increase hadron rejection. TOFino: angles below 45º. Scintillator rods. Time resol 350ps. Temporary. 1minuto 5 segundos TOF MDCs Shower Cross section of HADES Front view from inside

RPC wall Sectors are filled with RPC cells 80 times larger granularity The RPC wall contains 1024 double-sided readout cells (2048 channels) Acceptance close to 100% Double layer 80 times larger granularity Will allow collisions from C-C to Au-Au at 1.5GeV The image shows the way the RPC cells will be set up on each sector. It contains more than 1000 detector cells The RPC wall will allow 80 times larger granularity *****The time resolutions obtained are 70ps (5 times larger than the old detector) Counting rates of about 700hz/cm2 will allow collisions from C-C to Au-Au There are two layers of cells to increase the acceptance of the wall. 32 segundos Total: 2min y 54 segundos

Structure of the HADES RPC cells RPC Gas Box & cells(P. Fonte et al. LIP-Coimbra) CHEAP MATERIALS: Aluminium Glass SHIELDED CELLS: Crosstalk < 1% STANDARD GAS MIXTURE: Freon (85%) SF6 (15%) Isobutane (5%) This is the cross section structure of the cells. Formed with Al and Window glass (which are very cheap materials). Every cell is shielded to reduce the crosstalk. Levels measured are below 1%. It is a gaseus detector, containing Freon, SF6 and Isobutane, and works in avalanche mode. The design of the cells and the gas-box is performed in Coimbra by Paulo Fonte and his group. 37 segundos 3:34 Structure of the HADES RPC cells

OUTLINE INTRODUCTION TO HADES EXPERIMENT OVERVIEW OF TESTED ELECTRONICS FRONT-END ELECTRONICS DAUGHTERBOARD MOTHERBOARD READ OUT SYSTEM RESULTS CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS PLAN FOR THE NEXT TESTS

ELECTRONICS Front End Read out system TRB MB DB To ethernet RPC cells

ELECTRONICS Front End TRB MB DB To ethernet RPC cells

FRONT END ELECTRONICS Not enough number of channels to design an ASIC Built with commercially available components Space restrictions due to geometry Requires low power consumption to avoid heating problems INPUT: Short analog pulses (about 500ps rise time and 5ns width) from the RPC cells. Detector active area 50mV 100ns The Front End electronics requires a large bandwith due to the short rise times of the RPC pulses, It has low noise levels, to keep the cross talk levels provided by the RPC shielding Provides time resolutions below 100ps that will be corrected with the charge information to reduce this value to 70 ps LVDS output signals Has an trigger output signal Is built with commercially available components, there are size restrictions an the consume must be moderate to avoid heating problems. Electronic requirements: A large bandwidth to deal with the short rise times Low electronic jitter and noise for good time resolutions Front End set up on the RPC sector

DAUGHTERBOARD Takes analog signals from 2 RPC cells and provides a digital output pulses 4 electronic channels/board (two in each side) All SMT components (0603 size of R & C) 6 Layer board 4 2 4.5cm 1 2 3 4 5cm Back side Front side

DAUGHTERBOARD Generates a timing-signal (output pulse) . It contains information about: Arrival time (for TOF measurement)Leading edge Walk error Small walk error due to: -Small rise time Further reduction by: -Decreasing TOF thr. -Charge correction ChargeWidth(Trailing edge) Ideal correction width~charge Arrival time PECL comparator R Amplifier MAX9601-2ch (500ps Propagation Delay) 2k2 Trigger Out. Σ4ch. In Q Q/ BFT92 Wideband PNP Transistor OPA690 Wideband Op. Amplifier MAX9601-2ch ToT-Threshold Integrator C Latch enable Q Q/ C Latch enable The figure shows the block diagram of the daughterboard. First the RPC signal is amplified with a GHz bandwith amplifier. Then the circuit is divided in two branches: In one hand there is a single edge comparator for the detection of the arrival time of the RPC signal. On the other side there is a shaper, which is an integrator and after this other single edge comparator for the detection of the zero crossing of the integrated signal, thus determining the with of the output signal, which is proportional to the charge The charge comparator acts over the latch enable of the time comparator to keep the output latched until the desactivation of the second comparator GALI-S66 Monolithic (20dB, 2GHz) ToF-Threshold 4 ch. out PECL- LVDS SN65LVDT100 SAMTEC 16 diff. pins

DAUGHTERBOARD Integrated signal Amplified RPC signal Output pulse ƒ ToF xG RPC signal ƒ ToT Voltage (50mV/div) Integrated signal TOT thr RPC arrival time TOF thr The yellow trace shows the typical shape of an RPC signal. RPC signals have an amplitud from 1mv to 50mV and about 500ps rise time. The output of the FrontEnd electronics provides a pulse signal, where The leading edge gives information of the arrival time of the RPC signal and the width of the pulse provides information about the charge. We use two comparators to obtain this output signal. A single edge comparator acts over the amplified RPC to produce the rising edge when the RPC signal appears, a second comparator produces the trailing edge for width measurement. This is done with the time over threshold method, where the RPC signal is shaped through an integrator and a comparator with negative threshold that detects the zero crossing point of the integrated signal. This is performed by a board called Daughterboard Amplified RPC signal Output pulse width~charge Time (100ns/div)

MOTHERBOARD Part of the Front End Electronics that did not fit on the Daughterboard  interfaces DB with Readout system Provides support to 32 channels (8 DB) 12 layer board Connector to TRB LVDS conv +5V -5V +3.3V DC input Low level trigger (N to 1) Test signal distribution DC filter DC filter DC filter DC filter DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB DAC inverters Connector to DB

MOTHERBOARD Main tasks: 32 channels 12 Layer board 6cm 40cm Main tasks: Delivers the timing-signals from 8 Daughterboard to the Read out board. Supply stable voltage to the Daughterboards (+5V,-5V,+3.3V) Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal. Allocates DACs for the threshold voltages of the comparators on the Daugherboard Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC programming, etc

MOTHERBOARD Interface: Low Voltage Differential Signaling (LVDS) Advantages: Low power consumption High noise inmunity Diferential impedance matching lines and termination resistors (100Ω) to reduce signal reflections/distorsions

MOTHERBOARD Main tasks: 6cm 40cm Main tasks: Delivers the timing-signals from 8 Daughterboard to the Read out board. Supply stable voltages to the Daughterboards (+5V,-5V,+3.3V) Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal. Allocates DACs for the threshold voltages of the comparators on the Daugherboard Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC programming, etc

MOTHERBOARD Ripple filtering: Low Dropout Regulators DC-DC converter Motherboard +5V -5V ch1 +3.3V ch2 Noise filtering: Ferrite beads + low ESL capacitors +5V,+3.3V: ADP3338 (1A) -5V: LT1175 (0.5A) 1 regulator block every two channels ( from DC up to 10-200Kilohertz) MIN VOLTAGE DROP:~350mV MIN VOLTAGE DROP:~200mV

MOTHERBOARD Main tasks: 6cm 40cm Main tasks: Delivers the timing-signals from 8 Daughterboard to the Read out board. Supply stable voltages to the Daughterboards (+5V,-5V,+3.3V) Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal. Allocates DACs for the threshold voltages of the comparators on the Daugherboard Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC programming, etc

Rate < 1kHz/cm2 RPC area MOTHERBOARD Low level trigger output: Two-stage circuit Summing OPAMs OPA690 High slew rate High output swing -100mV contribution per channel Rate < 1kHz/cm2 RPC area x100cm2 =100kHz X31 channels = 3.1 MHz firing

MOTHERBOARD Main tasks: 6cm 40cm Main tasks: Delivers the timing-signals from 8 Daughterboard to the Read out board. Supply stable voltages to the Daughterboards (+5V,-5V,+3.3V) Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal. Allocates DACs for the threshold voltages of the comparators on the Daugherboard Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC programming, etc

MOTHERBOARD DAC thresholds Read out board Motherboard Programable by SPI 8 DAC chips/Motherboard 8 Channels/DAC chip Daisy-chained LTC2620 (12 bits resolution) Feedback for data transmission error detection Read out board DIN DO CS CLK Motherboard TTL to LVDS converter DAC1 DAC2 DAC8 LVDS to TTL converters

MOTHERBOARD Main tasks: 6cm 40cm Main tasks: Delivers the timing-signals from 8 Daughterboard to the Read out board. Supply stable voltages to the Daughterboards (+5V,-5V,+3.3V) Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal. Allocates DACs for the threshold voltages of the comparators on the Daugherboard Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC programming, etc

ELECTRONICS Read out system TRB MB DB To ethernet RPC cells

READ OUT SYSTEM TRB (TDC Readout Board): Custom board 4x32 channels HPTDC 80 pin twisted parir cable, KEL connector Single chip computer with ethernet (ETRAX) FPGA DC/DC 48V, isolated Memory TRB (TDC Readout Board): Custom board Based on the HPTDC ASIC developed at CERN 128-channel Front End HPTDC HPTDC HPTDC HPTDC The time readout board is a custom board that is used for time measurement. It is based on the HPTDC ASIC developed at CERN. It has 128 channels, but requires 1 of them for timing. It also contains a FPGA for, a single chip computer with ethernet, a DC/DC converter and memory. Board Controller FPGA Trigger bus Optional DSP processing LVL1 queue LVL2 queue CPU Ethernet GSI (M. Traxler et al.)

RESULTS Tests with gamma illumination using 60Co source: Full chain:Detector+FEE+TRB <0.5W/channel Crosstalk<1% Output width vs charge correlation for gamma illumination using 60Co source ToFThr=15mV ToTThr=-20mV Time of Flight measurements

Sector prototype with 48 channels RESULTS Test with RPC signals under C-C (1.5 GeV) collisions 80 ps Sector prototype with 48 channels 77 ps Crosstalk 2%-6%

OUTLINE INTRODUCTION TO HADES EXPERIMENT OVERVIEW OF TESTED ELECTRONICS FRONT-END ELECTRONICS DAUGHTERBOARD MOTHERBOARD READ OUT SYSTEM RESULTS CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS PLAN FOR THE NEXT TESTS

Charge comparator removed DAUGHTERBOARD Improved charge measurement Used a more gain preamplifier 2nd integration for linearity Only one comparator 30% power consumption reduction Discriminator Step R Amplifier Step MAX9601-2ch 500ps Propagation Delay 2k2 Trigger Out. Σ4ch. In Q Q/ BFT92 Wideband PNP Transistor C C The figure shows the block diagram of the daughterboard. First the RPC signal is amplified with a GHz bandwith amplifier. Then the circuit is divided in two branches: In one hand there is a single edge comparator for the detection of the arrival time of the RPC signal. On the other side there is a shaper, which is an integrator and after this other single edge comparator for the detection of the zero crossing of the integrated signal, thus determining the with of the output signal, which is proportional to the charge The charge comparator acts over the latch enable of the time comparator to keep the output latched until the desactivation of the second comparator Latch enable/ BGM1013 Monolithic (31dB, 2.2GHz) 4 ch. out ToF-Threshold PECL- LVDS C 2nd integration RC=20ns SN65LVDT100 OPA690 Wideband Op. Amplifier R SAMTEC 16 diff. pins ToT Integrator Charge comparator removed

DAUGHTERBOARD Benefits: linearity of the charge measurement (by adjusting integration values) More dynamic range Linear Saturation

MOTHERBOARD 2 only modifications: 6cm 40cm 2 only modifications: Addition of common mode filters at the power input Cooper area at the bottom ground improvement

Optional DSP processing READ OUT SYSTEM New general purpose Readout: Layout bugs corrected New FPGA (VIRTEX4) New DSP (TigerSharc) Detector independent: Also for PANDA & CBM Add-on board concept: 32 LVDS input lines Front End HPTDC HPTDC HPTDC HPTDC The time readout board is a custom board that is used for time measurement. It is based on the HPTDC ASIC developed at CERN. It has 128 channels, but requires 1 of them for timing. It also contains a FPGA for, a single chip computer with ethernet, a DC/DC converter and memory. Board Controller FPGA 32input LVDS lines Optical link (2Gbit/s) Optional DSP processing LVL1 queue LVL2 queue CPU Ethernet

OUTLINE INTRODUCTION TO HADES EXPERIMENT OVERVIEW OF TESTED ELECTRONICS FRONT-END ELECTRONICS DAUGHTERBOARD MOTHERBOARD READ OUT SYSTEM RESULTS CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS PLAN FOR THE NEXT TESTS

PLAN FOR NEXT TESTS FULL SECTOR TEST 350 channels Sector gas box ready. New electronics already developed. Produced: 12 MB & 4 miniMB 108 DB 4 TRB (Read out) Currently being assembled Gas box wiew without front cover

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