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Calorimeter upgrade meeting – CERN – October 5 th 2010 Analog FE ASIC: first prototype Upgrade of the front end electronics of the LHCb calorimeter E. Picatoste, A. Sanuy, D. Gascón Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB

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5/October/2010LHCb Upgrade2 Outline (1)Introduction (2)Current Mode Preamplifier (3)Integrator FDOA Switched Integrator (4)Linearity (5)Noise (6)IC Implementation Details

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5/October/2010LHCb Upgrade3 Introduction ECAL analogue FE IC: channel architecture Switched integrator Track and Hold First Prototype

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5/October/2010LHCb Upgrade4 Introduction IC sent: ICECAL Current preamp Integrators

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5/October/2010LHCb Upgrade5 Current mode preamplifier Pros: –“Natural” current processing –Lower supply voltage –All low impedance nodes: Pickup rejection –No external components –No extra pad Cons: –Trade-off in current mirrors: linearity vs bandwidth Low voltage –Only 1 Vbe for the super common base input stage Better in terms of ESD: –No input pad connected to any transistor gate or base Inner loop: lower input impedance Outer loop: control input impedance

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5/October/2010LHCb Upgrade6 Current mode preamplifier Simulations based on the extracted RC |Zin| Zin phase Gain+ Gain- Possible compensations: Parallel R current ladder |Gain| Gain phase Gain+ Gain-

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5/October/2010LHCb Upgrade7 Current mode preamplifier Simulations based on the extracted RC: linearity vs. I i,peak Gain+ Gain- Operation range

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5/October/2010LHCb Upgrade8 Current mode preamplifier Linearity error after integration (ideal) vs input charge

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5/October/2010LHCb Upgrade9 Integrator Switched integrator architecture FDOA FDOA specifications ParameterValue Gain bandwidth 500 MHz Phase margin> 65º Slew rate> 2 V/μs V CM 1.65 V CMOS switches

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5/October/2010LHCb Upgrade10 FDOA: design Fully differential Operational Amplifier Folded cascode NPN CE amp Pole compensation R Degenertion Common Mode Feedback

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5/October/2010LHCb Upgrade11 FDOA: open loop post layout simulations G LF (dB) BW (KHz) GBW (MHz) PM (º) G (dB) Phase (º) IbCE = 900uA Load capacitor between 150fF and 5.1pF

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5/October/2010LHCb Upgrade12 FDOA: closed loop post layout simulations IbCE = 900uA Load capacitor between 150fF and 5.1pF t rise (ns) overshoot SR (V/ns)

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5/October/2010LHCb Upgrade13 Integrator: pulse response Simulations based on extracted RC C l = 5pF V out (V) V int,ideal (V) V iD (mV) I in (mA)

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5/October/2010LHCb Upgrade14 Integrator: Linearity Simulations based on extracted RC C l = 5pF Error (%) V out (V)

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5/October/2010LHCb Upgrade15 Front End simulations (Preamp+integrator) Simulations based on extracted RC of complete IC Includes PM signal (TDR) and cable effects PM signal Clipping line cable Preamp + integrator

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5/October/2010LHCb Upgrade16 Front End simulation (Preamp+integrator) Simulations based on extracted RC of complete IC Includes PM signal (TDR) and cable effects V PM V oD2 V oD1 I PM I cable (clipped) ViVi

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5/October/2010LHCb Upgrade17 Front End simulation: linearity Dynamic deviation of the input impedance

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5/October/2010LHCb Upgrade18 Front End simulation: linearity VoD1 VoD2 Linear error

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5/October/2010LHCb Upgrade19 Noise after dynamic pedestal subtraction σ = 479 μV σ = 377 μV Noise Front End simulation: noise Transient noise analysis Integrator 1 output Clock Sampling time t 1 Sampling time t 2 Noise at output: distribution of V(t 2 ) Noise after dynamic pedestal subtraction: distributon of V(t 1 )- V(t 2 )

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5/October/2010LHCb Upgrade20 IC Implementation details AMS SiGe BiCMOS s35 QFN package –Substrate connected to central pad (gnd) When taking into account the bonding parasistics: –3 * nominal L ⇒ danger of ringing Solutions: –Include R in series with decoupling capacitor of Vref –Increase number of gnd pins –Downbonds for gnd Downbond

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5/October/2010LHCb Upgrade21 Prototype test PCB PCB designed for tests –4 layers –2 socket compatible –About 8x9 cm Chips arrived on 1st October.

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