1. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia R/O concept of the MVD demonstrator C.Schrader, S. Amar-Youcef, A. Büdenbender, M. Deveaux, D. Doering, J. Heuser, I. Fröhlich, J. Michel, C. Müntz, S. Seddiki, J. Stroth, T. Tischler, and B. Wiedemann

2. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Outline readout concept of the MVD demonstrator hardware components data processing first results of measurements subjects of this talk

3. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia 2x mimosa20 Overview of hardware components analogue output sync. signals data transfer: OP-link monitoring Demo-Aux-PCB MAPS add-on board Trb2 support flex-print-cable PC storage data transfer: in future: optical link (trb2) at present: I/O-card data transfer: I/O-card or

4. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Functionality of demo-Aux board demo- Aux board:  analogue buffers for pixel data transfer  low voltage regulated power supply for Mi20-chips  chip slow control wire JTAG  convert of the analogue temperature signals to analog LVDS signals  convert of the LVTTL sync. signals from M20-chip to digital LVDS signals 50 PIN SUB-D Con Flex-Con Flex-cable Mi20 Demo-Aux-board Mi20 MAPS add-on-board status of the demo-Aux: advanced schematics will be developed by IKF mimosa20:  4x analogue differential signal outputs for long-distance data transfer  LVTTL sync. signals for chip controlling  4x analogue signals for temperature monitoring < 5cm

5. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Functionality of the add-on board platform to study online data specification for data reduction close to hardware for chip integration in future times compatibility with HADES DAQ (Trb2) for testing purposes This data rate is too high for data storage systems online data reduction status: 12 layer board is completed and tested developed by IKF mimosa20 add-on board with a FPGA as reconfigurable hardware demonstrator: 2x mimosa, parallel readout, 360 x 640 pixel/frame, 50MHz  2.4Gbit/s, uncompressed CBM: ~2Gbit/s compressed see talk of S. Seddiki

6. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Components of the add-on-board  differential-to-differential amplifier to balance the analogue input for the ADCs  4 x 12bit ADCs to read out the analogue output signal of the two chips  LVDS differential drivers and receivers for chip controlling  Virtex IV LX 40 FPGA and memory banks for online data-processing  two high-speed connectors (15Gbit/s) for data transfer towards the Trb2-board 4x diff. analogue pixel data signals LVDS digital sync. signals add-on-board I/O from demo-Aux

7. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Trb2 and Add-on board concept Trb2 provides: high data-rate digital interface connector (15Gbit/s) FPGA configuration high data transfer with optical link (2Gbit/s), in future application process interface (API) power supply +5V,10A clock distribution the general-propose trigger and readout board (Trb2)  the Trb2 (HADES) has been designed in a way to be detector independent by using a flexible add-on board concept  the MAPS Add-on board is mounted on the Trb2 back side status: the Trb2-Add-on concept is in use

8. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Data processing processing steps: correlated double sampling (CDS) bit reduction threshold (for hit identification) cluster finding (the hit and the 8 neighbor pixels are important) pipelined algorithms for real-time application in stream mode zero suppression

9. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia ADC calibration devices intrinsic uncertainly : Integral Nonlinearity error (INL) = ±1.6LSB± 2LSB ADC OP... result: the difference of ideal and actual value is: ±2 ADC counts uncertainties are dominated by ADC readout chain is OK readout chain is OK calibration terms are included in data processing with error bars without error bars

10. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia First measurement results (mimosa20) marker pixel 32 µs digital sync. signals for chip controlling analogue raw pixel data converted by 12bit ADC measured sub matrix with pixel defects

11. C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia Project status Hardware: add-on board: design  manufacturing  test  I/O interface to PC side: installation  firmware development  test  odemo-Aux board: specification  ongoing design, manufacturing Nov2008 Data processing: VHDL: CDS  bit-reduction  threshold  data-output-interface  cluster finding (S. Seddiki)‏: specification  ongoing implementation data acquisition and storage software for PC : development  installation  test 

12. THANK YOU

13. readout cycle ADC units ∆ ADC acquisition cycle Fig.8: The behaviour of SB-pixels is observed by frames. The constant current leakage in the capacitor is compensate through a diode. After hit the diode re-fill the capacitor Fig.10: After CDS clear hit identification is possible f x :p x f x-1 :p x (f x :p x - f x-1 :p x )‏ (f x-1 :p x - f x-2 :p x )‏ hit Correlated double sampling by Self-Bias-Pixel Fig.9: Equivalent circuit diagram of SB-Pixel 1900 threshold

14. Threshold The hit and the 8 neighbour pixels are important Result: not the complete matrix is readout, only the hit with the neighbour pixel Fig.12: Data selection with threshold

15. Add-on board design Fig.11: Add-on board

16. bit-flipping RESULT: last bit is flipping constant power supply: ~503mV± 10µV % Digital code [ADC counts] % % % % % %