CEC 220 Digital Circuit Design VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Slide 1 of 13

Lecture Outline Wednesday, March 25 CEC 220 Digital Circuit Design Sequential Logic in VHDL Design of Registers & Counters in VHDL Slide 2 of 13

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Architecture Statements  All architecture statements execute concurrently Process Statements – Sequential execution  The Process statement executes when any signal in the sensitivity list changes architecture my_arc1 of my_box is signal sig1: bit; begin ?? <= ???; end my_arc1; process (CLK, …) begin ?? <= ???; end process; Slide 3 of 13 entity name

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Conditional Assignment Statements  Outside of process blocks (concurrent statements)  Inside process blocks (sequential statements) F <= IN0 when A = “00” else IN1 when A = “01” else IN2 when A = “10” else IN3; with A select F <= IN0 when A = “00”, IN1 when A = “01”, IN2 when A = “10”, IN3 when others; or if A = “00” then F <= IN0; elsif A = “01” then F <= IN1; elsif A = “10” then F <= IN2; else F <= IN3; end if; or case A is when “00” => F <= IN0; when “01” => F <= IN1; when “10” => F <= IN2; when others => F <= IN3; end case; Slide 4 of 13

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Modeling a Gated S-R LatchGated S-R Latch S Q G R process (G,S,R) begin if G=‘1’ then if S=‘1’ and R=‘0’ then Q<=‘1’; end if; if S=‘0’ and R=‘1’ then Q<=‘0’; end if; end if; end process; Gate lowHoldSetReset - Why is the S=0 & R=0 case not included? - What will Q be when S=1 & R=1 (from the code above)? Slide 5 of 13

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Modeling a Gated D LatchGated D Latch D Q G process (D, G) begin if G =‘1’ then Q <= D; end if; end process; Gate low Slide 6 of 13 Gate highGate low - Why is the G = ‘0’ case not included?

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Modeling a JK Flip-Flop with Async. Set & ResetJK Flip-Flop entity JKFF is port( J, K, SetN, RstN, CLK : in bit; -- inputs Q, QN: out bit); -- Q and QN are the outputs end JKFF; architecture JKFF_eqns of JKFF is signal Qint: bit; -- Internal value of Q begin Q <= Qint; QN <= not Qint; process(SetN, RstN, CLK) -- Asyncronous Set and Reset begin if RstN='0' then Qint <='0' after 5 ns; elsif SetN='0' then Qint <='1' after 5 ns; elsif CLK'event and CLK = '0' then -- falling edge of CLK Qint <= (J and not Qint) or (not K and Qint) after 10 ns; end if; end process; end JKFF_eqns ; Slide 7 of 13 - What will happen if RstN = ‘0’ & SetN = ‘0’ ? - Why are J & K not in the sensitivity list ?

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Modeling a JK Flip-Flop with Set & ResetJK Flip-Flop  A simulation example Slide 8 of 13 HoldSetToggleRNResetHoldSNToggle

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Modeling a 3-bit Rotating RegisterRotating Register entity DFF is port ( D, CLK : in bit; Q: out bit); end DFF; entity ROTATER is port ( clk: in bit; Qout: out bit_vector(0 to 2) :="100"); end ROTATER; architecture DFF_eqns of DFF is begin process(CLK) begin if CLK'event and CLK = '0' then Q <= D; end if; end process; end DFF_eqns; signal Q0, Q1, Q2: bit; begin FF0: DFF port map(Q2, CLK, Q0); FF1: DFF port map(Q0, CLK, Q1); FF2: DFF port map(Q1, CLK, Q2); Qout <= Q0 & Q1 & Q2; end ROTATING_REG; architecture ROTATING_REG of ROTATER is component DFF port ( D, CLK: in bit; Q: out bit); end component; CLK Initialization Slide 9 of 13

VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Simulation results  Q 0 Q 1 Q 2 was initialized to be “100” Slide 10 of

VHDL in Sequential Logic Using the IEEE Library Wednesday, March 25 CEC 220 Digital Circuit Design A 16-bit Up-Counter16-bit Up-Counter 16 Registers + 1 rstclk q library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port ( clk, rst: in std_logic; q: out std_logic_vector(15 downto 0)); end counter; architecture my_logic of counter is signal q_tmp: std_logic_vector(15 downto 0); begin process(clk, rst) begin if rst = '0' then q_tmp <= " "; elsif rising_edge(clk) then q_tmp <= q_tmp + 1; end if; end process; q <= q_tmp; end my_logic; The ‘+’ operator causes the generation of a 16-bit adder in hardware!! The “rising_edge” and “falling_edge” functions are defined in the IEEE Library Slide 11 of 13

VHDL in Sequential Logic Using the IEEE Library Wednesday, March 25 CEC 220 Digital Circuit Design A 16-bit Up-Counter16-bit Up-Counter 16 Registers + 1 rstclk q Slide 12 of 13

Next Lecture Wednesday, March 25 CEC 220 Digital Circuit Design Mealy and Moore State Machines Slide 13 of 13