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1 Sequential Logic Lecture #7. 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Shift Register Counter.

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Presentation on theme: "1 Sequential Logic Lecture #7. 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Shift Register Counter."— Presentation transcript:

1 1 Sequential Logic Lecture #7

2 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Shift Register Counter

3 모바일컴퓨팅특강 3

4 4 SR Latch Most simple “ storage element ”. Q next = (R + Q ’ current ) ’ Q ’ next = (S + Q current ) ’ In1In2Out 001 010 100 110 NOR Function Table Storing

5 모바일컴퓨팅특강 5 SR latches are sequential For inputs SR = 00, the next value of Q depends on the current value of Q. So the same inputs can yield different outputs. This is different from the combinational logics.

6 모바일컴퓨팅특강 6 Timing Diagram for S-R Latch S R Q Q’ SetReset

7 모바일컴퓨팅특강 7 SR latch simulation

8 모바일컴퓨팅특강 8 What about SR = 11? Both Q next and Q ’ next will become 0. If we then make S = 0 and R = 0 together, Q next = (0 + 0) ’ = 1 Q ’ next = (0 + 0) ’ = 1 But these new values go back into the NOR gates, and in the next step we get: Q next = (0 + 1) ’ = 0 Q ’ next = (0 + 1) ’ = 0 The logic enters an infinite loop, where Q and Q ’ cycle between 0 and 1 forever. (Unstable) This is actually the worst case, so we have to avoid setting SR=11. Q next = (R + Q’ current )’ Q’ next = (S + Q current )’ 0 0 0 0 0 0 1 1

9 모바일컴퓨팅특강 9 An SR latch with a control input (Gated SR latch) The dotted blue box is the S ’ R ’ latch from the previous slide. The additional NAND gates are simply used to generate the correct inputs for the S ’ R ’ latch. The control input acts just like an enable.

10 모바일컴퓨팅특강 10 D latch (Gated D latch) D latch is based on an S ’ R ’ latch. The additional gates generate the S ’ and R ’ signals, based on inputs D ( “ data ” ) and C ( “ control ” ). When C = 0, S ’ and R ’ are both 1, so the state Q does not change. When C = 1, the latch output Q will equal the input D. Single input for both set and reset Also, this latch has no “ bad ” input combinations to avoid. Any of the four possible assignments to C and D are valid.

11 모바일컴퓨팅특강 11 Timing diagram for D Latch Q follows D while EN is HIGH.

12 모바일컴퓨팅특강 12 D latch with BDF

13 모바일컴퓨팅특강 13 D latch simulation with Primitive Insert the symbol latch

14 모바일컴퓨팅특강 14 Simulation result with Primitive

15 모바일컴퓨팅특강 15 D latch simulation with VHDL file

16 모바일컴퓨팅특강 16 The D Flip-Flop : Edge triggering The D flip-flop is said to be “edge triggered” since the output Q only changes on the rising edge (positive edge) of the clock signal D Latch D1 C Q1 Q’ D Latch D2 C Q2 Q2’ D C Q

17 모바일컴퓨팅특강 17 Timing Diagram for a D-FF C D Q Q1 shift Positive Edge Triggering

18 모바일컴퓨팅특강 18 D-FF with Direct Inputs Most flip-flops provide direct, or asynchronous, inputs that immediately sets or clears the state. The below is a D flip-flop with active-low direct inputs. Direct inputs to set or reset the flip-flop S’R’ = 11 for “normal” operation of the D flip-flop

19 모바일컴퓨팅특강 19 D-FF with BDF Insert the symbol dff Edge-trigger symbol

20 모바일컴퓨팅특강 20 D-FF with VHDL file

21 모바일컴퓨팅특강 21 D-FF with active-high Clock & asynchronous Clear library ieee; use ieee.std_logic_1164.all; entity dff_1 is port( d, clk, nclr : in std_logic; q : out std_logic ); end dff_1 ; architecture a of dff_1 is begin process(nclr,clk) begin if( nclr='0') then q <='0'; elsif(clk'event and clk='1') then q <= d; end if; end process; end a;

22 모바일컴퓨팅특강 22 D-FF with active- low Clock & asynchronous Clear library ieee; use ieee.std_logic_1164.all; entity dff_fall_1 is port( d, clk, nclr : in std_logic; q : out std_logic ); end dff_fall_1 ; architecture a of dff_fall_1 is begin process(nclr,clk) begin if( nclr='0') then q <='0'; elsif(clk'event and clk=‘0') then q <= d; end if; end process; end a;

23 모바일컴퓨팅특강 23 D-FF with active-high Clock & asynchronous Preset library ieee; use ieee.std_logic_1164.all; entity dff_ preset_1 is port( d, clk, npre : in std_logic; q : out std_logic ); end dff_ preset_1 ; architecture a of dff_ preset_1 is begin process(npre,clk) begin if( npre='0') then q <=‘1'; elsif(clk'event and clk=‘1') then q <= d; end if; end process; end a;

24 모바일컴퓨팅특강 24 D-FF with active-high Clock & asynchronous Clear & Preset library ieee; use ieee.std_logic_1164.all; entity dff_ presetclr_1 is port( d, clk, npre,nclr : in std_logic; q : out std_logic ); end dff_ presetclr_1 ; architecture a of dff_ presetclr_1 is begin process(npre, nclr, clk) begin if( npre='0') then q <=‘1'; elsif( nclr='0') then q <=‘0'; elsif(clk'event and clk=‘1') then q <= d; end if; end process; end a;

25 모바일컴퓨팅특강 25 JK-FF & T-FF JK=11 are used to complement the flip-flop ’ s current state. A T flip-flop can only maintain or complement its current state.

26 모바일컴퓨팅특강 26 7474 Dual D-FF Insert the symbol others > quartus II > 7474

27 모바일컴퓨팅특강 27 7474 Dual D-FF “Datasheet” from Philips Plastic dual in-line package

28 모바일컴퓨팅특강 28 7474 Dual D-FF “Datasheet” from Philips

29 모바일컴퓨팅특강 29 Set-up and hold times For proper operation the D input to a D flip-flop should be stable for certain prescribed times before and after the rising clock edge. These are referred to as the set-up and hold times respectively

30 모바일컴퓨팅특강 30 Set-up time (t s ) The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

31 모바일컴퓨팅특강 31 Hold time (t h ) The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

32 모바일컴퓨팅특강 32 D-FF timing constraints Set-up time Hold time C D Q Propagation delay

33 모바일컴퓨팅특강 33 Propagation Delay (1) As with any other circuit there will be a propagation delay between the rising edge of the clock and the time that the outputs of the flip-flop are stable.

34 모바일컴퓨팅특강 34 Propagation delay (2)

35 모바일컴퓨팅특강 35 7474 Timing characteristics from datasheet

36 모바일컴퓨팅특강 36 Clock Signal Periodic signal, generated by an oscillator which acts as the heartbeat of a synchronous digital system Clock Period Clock Frequency = 1 / Clock Period

37 모바일컴퓨팅특강 37 Synchronous Systems In a synchronous system, all of the state elements are connected to the same clock signal. This means that they all change state at the same time.

38 모바일컴퓨팅특강 38 Propagation delays through logic components (gates) through interconnects (routing delays) t p gates t p routing Gates Total propagation delay through combinational logic Timing Characteristics (1)

39 모바일컴퓨팅특강 39 Total propagation delay of logic (Sum of t p gate ) depends on the number of logic levels and delays of logic components Number of logic levels is the number of logic components (gates) the signal propagates through Routing delays (t p routing ) depend on: Length of interconnects Fanout Timing Characteristics (2)

40 모바일컴퓨팅특강 40 Fanout – Number of inputs connected to one output Each inputs has its capacitance Fast switching of outputs with high fanout requires higher currents  This makes a larger delay. Gates Timing Characteristics (3)

41 모바일컴퓨팅특강 41 In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays Timing Characteristics (4)

42 Critical path: the slowest path between any two storage devices Cycle time is a function of the critical path must be greater than: Clock-to-Q + Longest Path through Combinational Logic + Setup Clk........................ Critical Path & Cycle Time

43 모바일컴퓨팅특강 43 Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period Critical Path

44 모바일컴퓨팅특강 44 Rising Edge of The Clock Does Not Occur Precisely Periodically May cause faults in the circuit clk Clock Jitter

45 모바일컴퓨팅특강 45 Clock Skew Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time DQ in clk DQ out delay DQ in clk DQ out delay

46 모바일컴퓨팅특강 46 Dealing With Clock Problems Use Only Dedicated Clock Nets for Clock Signals Do Not Put Any Logic in Clock Nets

47 모바일컴퓨팅특강 47 Register Flip-Flip 을 응용한 데이터 저장장치 가장 기본적인 순차논리회로 Multi-bit Register Shift Register Counter Register

48 모바일컴퓨팅특강 48 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` Resetn Clock reg8 88 DQ 8-bit register with asynchronous reset

49 모바일컴퓨팅특강 49 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Resetn Clock regn NN DQ N-bit register with asynchronous reset

50 모바일컴퓨팅특강 50 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Q D Enable Clock regn NN N-bit register with Enable

51 모바일컴퓨팅특강 51 Shift register DQ Sin Clock DQDQDQ Q(3) Q(2) Q(1)Q(0) Enable

52 모바일컴퓨팅특강 52 Shift Register With Parallel Load D(3) DQ Clock Enable Sin D(2) DQ D(1) DQ D(0) DQ Q(0)Q(1)Q(2)Q(3) Load

53 모바일컴퓨팅특강 53 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; Q Enable Clock shift4 4 D Load Sin 4 4-bit shift register with parallel load (1)

54 모바일컴퓨팅특강 54 ARCHITECTURE Behavior_1 OF shift4 IS BEGIN PROCESS (Clock) BEGIN IF Clock'EVENT AND Clock = '1' THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Q(0) <= Q(1) ; Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin; END IF ; END PROCESS ; END Behavior_1 ; Q Enable Clock shift4 4 D Load Sin 4 4-bit shift register with parallel load (2)

55 모바일컴퓨팅특강 55 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ; Q Enable Clock shiftn N D Load Sin N N-bit shift register with parallel load (1)

56 모바일컴퓨팅특강 56 ARCHITECTURE Behavior OF shiftn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= Sin ; END IF; END PROCESS ; END Behavior ; Q Enable Clock shiftn N D Load Sin N N-bit shift register with parallel load (2)

57 모바일컴퓨팅특강 57 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT (Clear, Clock: IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" ; ELSE Q <= Q + “01” ; END IF ; END PROCESS; END Behavior ; Q Clear Clock upcount 2 2-bit up-counter with synchronous reset

58 모바일컴퓨팅특강 58 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; Q Enable Clock upcount 4 Resetn 4-bit up-counter with asynchronous reset (1)

59 모바일컴퓨팅특강 59 ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; END PROCESS ; Q <= Count ; END Behavior ; Q Enable Clock upcount 4 Resetn 4-bit up-counter with asynchronous reset (2)

60 모바일컴퓨팅특강 60 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt161_4bits is port( d3,d2,d1,d0 : in std_logic; nld,ent,enp : in std_logic; clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic; rco : out std_logic); end cnt161_4bits; architecture a of cnt161_4bits is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) variable d : std_logic_vector(3 downto 0); begin d := d3&d2&d1&d0; if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if(nld='0') then q <= d; elsif(ent='1' and enp='1') then q <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); rco <= ent and q(3) and q(2) and q(1) and q(0); end a; 74161 은 실제로 가장 널리 사용되는 4 비트 카운터임 4 bits Universal Counter: 74161

61 모바일컴퓨팅특강 61 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod16cnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod16cnt; architecture a of mod16cnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then q <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; Modulo 16 Up Counter

62 모바일컴퓨팅특강 62 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod16dncnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod16dncnt; architecture a of mod16dncnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then q <= q-'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; Modulo 16 Down Counter

63 모바일컴퓨팅특강 63 Modulo 16 Up Down counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity UpDncnt4 is port( clk,nclr: in std_logic; UpDn: in std_logic; q3,q2,q1,q0 : out std_logic); end UpDncnt4; architecture a of UpDncnt4 is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if( UpDn='1') then q <= q+'1'; else q <= q-'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; 1 이 면 증 가 0 이면 감소

64 모바일컴퓨팅특강 64 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod15cnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod15cnt; architecture a of mod15cnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if( q="1110") then q<="0000"; elseq <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; 14 에서 0 으로 증가 Modulo 15 Up Counter

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