1. Sequential statements (1) process
[process_name:] PROCESS (sensitivity list)
BEGIN
sequential statements
END PROCESS [process_name];

2. COMBINATIONAL PROCESS
PROCESS(a, b, c)
BEGIN
d <= (a AND b) OR c;
END PROCESS;
ALL input signals must be in sensitivity list or latches will be produced!

3. If statement (sequential)– describing MUXs
If condition1 then
signal1 <= value1;
signal2 <= value2;
elsif condition2 then
signal1 <= value3;
signal2 <= value4; …
[ELSE
signal1 <= valuen-1;
signal2 <= valuen;]
end if;
ENTITY mux IS
PORT (i0: in std_logic;
i1: in std_logic;
s: in std_logic;
o: out std_logic);
END mux;
ARCHITECTURE rtl OF mux IS
BEGIN
process(i0, i1, s)
If s = ‘0’ then
o <= i0;
else
o <= i1;
end if;
end process;
END rtl;

4. CASE statement (sequential)– describing MUXs
ENTITY mux IS
PORT (i0: in std_logic;
i1: in std_logic;
s: in std_logic;
o: out std_logic);
END mux;
ARCHITECTURE rtl OF mux IS
BEGIN
process(i0, i1, s)
CASE s IS
WHEN ‘0’ =>
o <= i0;
WHEN OTHERS =>
s <= i1;
end CASE;
end process;
END rtl;
CASE expression IS
when value1 =>
signal1 <= value2;
signal2 <= value3;
when value4 =>
signal1 <= value4;
signal2 <= value5;
. . .
[when others =>
signal1 <= valuen-1;
signal2 <= valuen;]
end CASE;

5. Example
Describe a 3-bit 4-to-1 MUX

6. CLOCKED PROCESS (Latch with asynchronous reset)
PROCESS(clk, rst_n)
BEGIN
IF rst_n = ‘0’ THEN
q <= (others => ‘0’);
ELSIF clk= ‘1’ THEN
q <= d;
END IF;
END PROCESS;

7. CLOCKED PROCESS (Latch with synchronous reset)
PROCESS(clk)
BEGIN
IF clk = ‘1’ THEN
if rst_n = ‘0’ then
q <= (others => ‘0’);
else q <= d;
end if;
END IF;
END PROCESS;

8. CLOCKED PROCESS (Flip-flop with asynchronous reset)
PROCESS(clk, rst_n)
BEGIN
IF rst_n = ‘0’ THEN
q <= (others => ‘0’);
ELSIF clk’event and clk= ‘1’ THEN
q <= d;
END IF;
END PROCESS;

9. CLOCKED PROCESS (Flip-flop with synchronous reset)
PROCESS(clk)
BEGIN
IF clk’event and clk= ‘1’ THEN
IF rst_n = ‘0’ THEN
q <= (others => ‘0’);
else q <= d;
end if;
END IF;
END PROCESS;

10. for loop statement – shift register
[label]: for identifier in range loop
statements
end loop;
ENTITY shift_reg is
port(clk, rst_n: in std_logic;
input: in std_logic;
output: out std_logic);
end shift_reg;
Architecture rtl of shift_reg is
signal d: std_logic_vector(3 downto 0);
begin
process(clk, rst_n)
if rst_n = ‘0’ then
d <= (others => ‘0’);
elsif rising_edge(clk) then
d(0) <= input;
for i in 0 to 3 loop
d(i+1) <= d(i);
end loop;
end if;
end process;
output <= d(3);
end;

11. CLOCKED VS COMBINATIONAL PROCESS (1/2)
process(clk, rst)
BEGIN
If rst = ‘1’ then
q <= ‘0’;
elsif clk’event and clk = ‘1’ then
CASE c IS
WHEN ‘0’ =>
q <= a;
WHEN OTHERS =>
q <= b;
end CASE;
end if;
end process;
process(a, b, c)
BEGIN
CASE c IS
WHEN ‘0’ =>
q <= a;
WHEN OTHERS =>
q <= b;
end CASE;
end process;

12. CLOCKED VS COMBINATIONAL PROCESS (2/2)
PROCESS(a, b, c)
BEGIN
d <= (a AND b) OR c;
END PROCESS;
PROCESS(clk, rst)
BEGIN
if rst = ‘1’ then
d <= ‘0’;
elsif clk’event and clk= ‘1’ then
d <= (a AND b) OR c;
end if;
END PROCESS;

13. EXAMPLE: BINARY UPCOUNTER
PROCESS(clk)
begin
if clk’event and clk=‘1’ then
if rst_n = ‘0’ then –-synchronous reset
count <= (others => ‘0’);
else
if en = ‘1’ then count enable
count <= count + ‘1’;
end if;
end process;

14. EXAMPLE
DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZERO

15. The integer type
Signal signal_name: integer range range_low to range_high
Examples:
Signal count: integer range 0 to bit counter
Signal k: integer range 0 to bit counter

16. Binary up counter ver2 ARCHITECTURE rtl of counter is
signal count: integer range 0 to 31; -- 5-bit counter
begin
PROCESS(clk)
if clk’event and clk=‘1’ then
if rst_n = ‘0’ then –-synchronous reset
count <= 0;
else
if en = ‘1’ then count enable
count <= count + 1;
end if;
end process;
end;

17. TESTBENCH Entity testbench_name is end testbench_name;
ARCHITECTURE architecture_name of testbench_name IS
COMPONENT declaration
Signal declaration --signal clk: std_logic:=‘0’;
BEGIN
Component instantiation
{ clk <= not clk after 40 ns; ns clock period
a <= ‘1’,
‘0’ after 50 ns,
‘1’ after 100 ns; }
end;

18. TESTBENCH EXAMPLE Entity testbench is end testbench;
begin
U_mux: mux
port map ( i0 =>i0, i1=>i1, s=>s, o=> o);
i0 <= ‘0’,
‘1’ after 50 ns,
‘0’ after 100 ns,
‘1’ after 150 ns,
‘0’ after 200 ns,
‘1’ after 250 ns,
‘0’ after 300 ns,
‘1’ after 350 ns;
i1 <= ‘0’,
‘1’ after 100 ns,
‘1’ after 300 ns;
s <= ‘0’,
‘1’ after 200 ns;
end test;
Entity testbench is
end testbench;
Architecture test of testbench is
component mux
PORT (i0: in std_logic;
i1: in std_logic;
s: in std_logic;
o: out std_logic);
END component;
signal i0, i1, s, o: std_logic;

19. FINITE STATE MACHINES

20. FINITE STATE MACHINE IMPLEMENTATION

21. Mealy machines (1/3) ENTITY fsm is
port(clk, rst_n, a, b: in std_logic;
o: out std_logic);
END ENTITY fsm;
ARCHITECTURE rtl of fsm is
Type state is (state0, state1);
Signal state_pr, state_nx: state;

22. Mealy machines (2/4) BEGIN Process(clk, rst_n) --sequential part begin
if (rst_n=‘0’) then
state_pr <= state0; --default state
elsif rising_edge(clk) then
state_pr <= state_nx;
end if;
end process;

23. Mealy machines (3/4) process(a, state_pr) --combinational part begin
CASE state_pr is
WHEN state0 =>
if (a = ‘1’) then
state_nx <= state1;
output <= <value>;
else
state_nx <= state0; --optional
end if;

24. Mealy machines (4/4) WHEN state1 => if (a = ‘1’) then
state_nx <= state0;
output <= <value>; --Mealy machine
else
state_nx <= state1; --optional
output <= <value>; --Mealy machine
end if;
end CASE;
end process;

25. Moore machines process(a, state_pr) --combinational part begin
CASE state_pr is
WHEN state0 =>
output <= <value>; Moore machine
if (a = ‘1’) then
state_nx <= state1;
else
state_nx <= state0; --optional
end if;

26. MOORE MACHINES WHEN state1 =>
output <= <value>; --Moore machine
if (a = ‘1’) then
state_nx <= state0;
else
state_nx <= state1; --optional
end if;
end CASE;
end process;

27. EXAMPLE: OUT-OF-SEQUENCE COUNTER
DESCRIBE A COUNTER WITH THE FOLLOWING SEQUENCE:
“000” => “010” => “011” => “001” => “111” => “000”