1.  Seattle Pacific University EE 1210 - Logic System DesignCounters-1 Shift Registers DQ clk DQ DQ ShiftIn Q3Q3 Q2Q2 DQ Q1Q1 Q0Q0 A shift register shifts all bits one to the right (or left) each clock period ????0 0???1 10??0 010?00010110011 0100 1001 0011 ?010 ??01 ???0 ???? Q0Q0 Q1Q1 Q2Q2 Q3Q3 Shift registers are useful for converting serial (one bit at a time) data to parallel (multiple bits at a time)

2.  Seattle Pacific University EE 1210 - Logic System DesignCounters-2 Ripple Counter ‘1’ C0C0 C1C1 C2C2 Clock C1C1 C2C2 clock C0C0 010101 A 3-bit asynchronous counter 001100000011 Note the cumulative delays in changing of bits T Q Q T Q Q T Q Q C2C2 C1C1 C0C0 000 001 010 011 100 101 110 111 When one bit changes from one to zero, next bit should toggle

3.  Seattle Pacific University EE 1210 - Logic System DesignCounters-3 Synchronous Counter ‘1’ T Q Q C0C0 T Q Q C1C1 T Q Q C2C2 Clock C1C1 C0C0 A 3-bit synchronous counter C2C2 000001010011100101 Note that all bits change at the same time clock C0C0 C0C0 C1C1 C2C2 C1C1 C0C0 000 001 010 011 100 101 110 111 When previous bits are all ones, next bit should toggle

4.  Seattle Pacific University EE 1210 - Logic System DesignCounters-4 General Binary Counters Q[7..0] CLK D[7..0] EN LD CLR 8-bit Counter Q – Count Value (Output) Edge-triggered clock D – Parallel load value LD – Parallel load EN – Count enable CLR – Set to zero Load and CLR may be synchronous or asynchronous

5.  Seattle Pacific University EE 1210 - Logic System DesignCounters-5 A Modulus N+1 Counter Q[7..0] CLK EN SCLR 8-bit Counter Whenever count >= N, clear counter Compare A[7..0] B[7..0] A>=B N ‘1’ CLK 0,1,2,3,4,…,N,0,1,2,… Requires synchronous clear

6.  Seattle Pacific University EE 1210 - Logic System DesignCounters-6 A Clock divider Q[19..0] CLK EN SCLR 20-bit Counter Count clock ticks  When reach 1,000,000, clear counter Compare A[19..0] B[19..0] A>=B 1,000,000 ‘1’ 1 MHz CLK Convert a 1MHz clock into a 1Hz clock by dividing by 1,000,000 1 Hz CLK Counter must have enough bits to reach compare value (1,000,000) WARNING: Clock is unbalanced: On for 1us, off for 999,999us

7.  Seattle Pacific University EE 1210 - Logic System DesignCounters-7 A Balanced Clock divider Q[19..0] CLK EN SCLR 20-bit Counter Compare A[19..0] B[19..0] A>=B 500,000 ‘1’ 1 MHz CLK Convert a 1MHz clock into a 50% duty cycle 1Hz clock by dividing by 500,000 and toggling output 2 Hz Unbalanced CLK T Q Q 1 MHz CLK 1 Hz 50% d.c. clock Toggle clock every 0.5s (500,000 clock cycles)

8.  Seattle Pacific University EE 1210 - Logic System DesignCounters-8 VHDL for a simple counter LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY count8 IS PORT( CLK : IN STD_LOGIC; EN: IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END count8; ARCHITECTURE behavior OF count8 IS SIGNAL Count: STD_LOGIC_VECTOR(7 DOWNTO 0)); BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN IF (EN=‘1’) THEN Count <= Count+1; ELSE Count <= Count; END IF; END IF; END PROCESS; Q <= Count; END behavior; Inputs: CLK and en Output: Q (eight bits) Requires an internal signal for the count (can’t use the output Q for this) If enabled, increment count; if not, don’t change it Note: Need unsigned library to do math Assign the output (Q) the value of count

9.  Seattle Pacific University EE 1210 - Logic System DesignCounters-9 Synch and Asynch Controls ARCHITECTURE behavior OF count8LC IS SIGNAL Count: STD_LOGIC_VECTOR(7 DOWNTO 0)); BEGIN PROCESS(CLK,CLR) BEGIN IF (CLR=‘1’) THEN Count <= “00000000”; ELSIF RISING_EDGE(CLK) THEN IF (LOAD = ‘1’) THEN Count <= D; ELSIF (EN=‘1’) THEN Count <= Count + 1; ELSE Count <= Count; END IF; END IF; END PROCESS; Q <= Count; END behavior; Add a synchronous load and an asynchronous clear Since CLR may come at any time, add to PROCESS LOAD only happens on rising edge  inside check for rising edge Note: Entity not shown due to space limitations CLR is outside of check for rising edge