1. History TTL-logic PAL (Programmable Array Logic)
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
TTL-logic
PAL (Programmable Array Logic)
FPGA (Field Programmable Gate Array) 1

2. FPGA Introduction Logical element / slice
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Logical element / slice
Programmable interconnections
RAM, DSP, PLL, IO, … 2

3. FPGA Structure Look-up table [ F’=f(F1,F2,F3,F4) ] Flip-flop
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Look-up table [ F’=f(F1,F2,F3,F4) ]
Flip-flop
Multiplexer 3

4. FPGA Overview LC’s Various Virtex family Spartan family Various
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
LC’s
Various
Virtex family
Spartan family
Various
Stratix family
Cyclone family
I/O
RAM bits 4

5. VHDL Introduction VHDL (VHSIC Hardware Description Language)
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
VHDL (VHSIC Hardware Description Language)
VHSIC (Very High Speed Integrated Circuit)
Original: Language for description, simulation and documentation of digital systems
Now: Language for description, simulation, documentation and syntheses of digital systems
First developments around 1970
First standardization in 1987 by IEEE (IEEE )
Later adjusted in 1993 (VHDL-93)
Again adjusted in 2001 (VHDL-2001)
Other languages (Verilog, Abel, ..) are available 5

6. Structure Component (inputs, outputs, behaviour)
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Component (inputs, outputs, behaviour)
Entity, architecture, signals 6

7. Language XOR function entity XORport is port ( A,B: in BIT; C: out BIT
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
XOR function
entity XORport is
port (
A,B: in BIT;
C: out BIT );
end XORport;
architecture dataflow of XORport is
begin
C<=A xor B;
end dataflow; 7

8. Language Template architecture architecture-name of entity-name is
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
architecture architecture-name of entity-name is
variable declarations
signal declarations
constant declarations
function definitions
component declarations
begin
concurrent-statement; …
end architecture-name;
entity entity-name is
port (
signal-names : mode signal-type; …
signal-names : mode signal-type );
end entity-name; 8

9. Signals Signal Variable Constant std_logic type: Signal-types:
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Signal
Physical value
Line or register in design
Has history of values
Can be observed in simulation
Variable
Temporally value
Only defined in process, block, procedure, function
Used to make design more readable
Can’t be observed in simulation
Constant
Used in generic programming
std_logic type:
‘U’ --Not initialized
‘X’ --Forcing Unknown
‘0’ --Forcing 0
‘1’ --Forcing 1
‘Z’ --High Impedance
‘W’ --Weak Unknown
‘L’ --Weak 0
‘H’ --Weak 1
‘-’ --Don’t care
Signal-types:
bit (‘1’ or ‘0’)
bit_vector (combination of bits)
boolean (‘true’ or ‘false’)
integer ( to )
real
user-defined types (defined by libraries)
std_logic
std_logic_vector
Problems with bit signal-types:
Unknown values
Don’t care
Pull-up or pull-down
Tri-state
Signal-modes: in
out
buffer
inout 9

10. Dataflow C<=A xor B; Q<=R nor nQ nQ<=S nor Q Q<=R nor nQ
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Q<=R nor nQ
nQ<=S nor Q
start : R='0', S='0', Q='1', nQ='0‘
step 1: R='1', S='0', Q='1', nQ='0‘ (Assert R)
step 2: R='1', S='0', Q='0', nQ='0‘ (Q changes)
step 3: R='1', S='0', Q='0', nQ='1‘ (nQ changes)
step 4: R=‘1', S='0', Q='0', nQ='1‘ (no changes => stop)
C<=A xor B;
Defines direct relation between output and input
Sequence not important (parallelism)
Asynchronous
Difficult for complex functions
Difficult to understand
Q<=R nor nQ
nQ<=S nor Q 10

11. Behavioural Sequence important Asynchronous
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Sequence important
Asynchronous
Divides complex functions in manageable parts
Easier to understand
case (signal-name) is
when condition =>
action1;
...
when others =>
action2;
end case;
for variable/signal-name in start-value to stop-value loop
action;
end loop;
process(signal-names)
begin
-- sequential code:
e.g.: if (condition) then
action1;
else
action2;
end if;
end process;
if (condition) then
action1;
elsif (condition) then
action2;
...
else
action3;
end if; 11

12. Structural Divide problems into sub-problems Connecting blocks Reuse
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
--component declarations
component entity-name
port (
signal-names : mode signal-type );
end component; …
--signals to connect blocks
signal-names : mode signal-type;
begin
component-name : component
port map (
signal-mapping ); …
Divide problems into sub-problems
Connecting blocks
Reuse 12

13. Synchronous Signals Rising or falling edge No ‘else’ condition
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
process(clk)
begin
if (clk'EVENT and clk='1') then
action;
end if;
end process;
Rising or falling edge
No ‘else’ condition
Clock signal in process list 13

14. Simulation Test functionality of each block
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Test functionality of each block
Test interaction between blocks
Test bench written in VHDL
Assert stimuli, observe outputs
Possible to look at internal signals 14

15. Design Flow Create new project Select FPGA device Create new VHDL file
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Create new project
Select FPGA device
Create new VHDL file
Simulation
Assign pins
Synthesis and fitting
Program device
Test new hardware 15

16. Example Quiz buttons (2 players, first push wins, reset)
History
FPGA introduction
FPGA structure
FPGA overview
VHDL introduction
Structure
Language
Language template
Signals
Dataflow
Behavioural
Structural
Synchronous signals
Simulation
Design flow
Example
Quiz buttons (2 players, first push wins, reset)
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tstbench is
end tstbench;
architecture test of tstbench is
component QuizButton is
port (
button1, button2: in std_logic;
reset: in std_logic;
light1, light2: out std_logic );
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal testData : std_logic_vector(1 downto 0) := "00";
begin …
uut: QuizButton port map (
button1=>testData(0), button2=>testData(1), reset=>rst
end test;
architecture dataflow of QuizButton is
signal state1 : std_logic := '0';
signal state2 : std_logic := '0';
begin
process(button1, button2, reset)
if (button1='1' and state2='0') then
state1<='1';
end if;
if (button2='1' and state1='0') then
state2<='1';
if (reset='1') then
state1<='0'; state2<='0';
end process;
light1<=state1;
light2<=state2;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity QuizButton is
port (
button1, button2: in std_logic;
reset: in std_logic;
light1, light2: out std_logic );
end QuizButton;
process(clk)
begin
clk <= not clk after 20 ns; -- 50MHz
if (clk='0') then
rst<='1';
else
rst<='0';
testData<="00";
testData<=testData+1 after 10 ns;
end if;
end process; 16