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1 Sequential Logic Lecture #7. 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Active-high Clock & asynchronous Clear Active-low Clock & asynchronous Clear Active-high.

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Presentation on theme: "1 Sequential Logic Lecture #7. 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Active-high Clock & asynchronous Clear Active-low Clock & asynchronous Clear Active-high."— Presentation transcript:

1 1 Sequential Logic Lecture #7

2 모바일컴퓨팅특강 2 강의순서 Latch FlipFlop Active-high Clock & asynchronous Clear Active-low Clock & asynchronous Clear Active-high Clock & asynchronous Preset Active-high Clock & asynchronous Clear & Preset Shift Register Counter 4 bits Universal Counter : 74161 Modulo 16 Up counter Modulo 16 Down counter Modulo 16 Up Down counter 0-14 hold Up counter

3 모바일컴퓨팅특강 3

4 4 SR Latch Most simple “ storage element ”. Q next = (R + Q ’ current ) ’ Q ’ next = (S + Q current ) ’ In1In2Out 001 010 100 110 NOR Function Table Storing

5 모바일컴퓨팅특강 5 SR latches are sequential For inputs SR = 00, the next value of Q depends on the current value of Q. So the same inputs can yield different outputs. This is different from the combinational logics.

6 모바일컴퓨팅특강 6 Timing Diagram for S-R Latch S R Q Q’ SetReset

7 모바일컴퓨팅특강 7 SR latch simulation

8 모바일컴퓨팅특강 8 What about SR = 11? Both Q next and Q ’ next will become 0. If we then make S = 0 and R = 0 together, Q next = (0 + 0) ’ = 1 Q ’ next = (0 + 0) ’ = 1 But these new values go back into the NOR gates, and in the next step we get: Q next = (0 + 1) ’ = 0 Q ’ next = (0 + 1) ’ = 0 The logic enters an infinite loop, where Q and Q ’ cycle between 0 and 1 forever. (Unstable) This is actually the worst case, so we have to avoid setting SR=11. Q next = (R + Q’ current )’ Q’ next = (S + Q current )’ 0 0 0 0 0 0 1 1

9 모바일컴퓨팅특강 9 An SR latch with a control input (Gated SR latch) The dotted blue box is the S ’ R ’ latch from the previous slide. The additional NAND gates are simply used to generate the correct inputs for the S ’ R ’ latch. The control input acts just like an enable.

10 모바일컴퓨팅특강 10 D latch (Gated D latch) D latch is based on an S ’ R ’ latch. The additional gates generate the S ’ and R ’ signals, based on inputs D ( “ data ” ) and C ( “ control ” ). When C = 0, S ’ and R ’ are both 1, so the state Q does not change. When C = 1, the latch output Q will equal the input D. Single input for both set and reset Also, this latch has no “ bad ” input combinations to avoid. Any of the four possible assignments to C and D are valid.

11 모바일컴퓨팅특강 11 Timing diagram for D Latch Q follows D while EN is HIGH.

12 모바일컴퓨팅특강 12 D latch with BDF

13 모바일컴퓨팅특강 13 D latch simulation with Primitive Insert the symbol latch

14 모바일컴퓨팅특강 14 Simulation result with Primitive

15 모바일컴퓨팅특강 15 D latch simulation with VHDL file

16 모바일컴퓨팅특강 16 The D flip-flop : Edge triggering The D flip-flop is said to be “edge triggered” since the output Q only changes on the rising edge (positive edge) of the clock signal D Latch D1 C Q1 Q’ D Latch D2 C Q2 Q2’ D C Q

17 모바일컴퓨팅특강 17 Timing Diagram for a D flip-flop C D Q Q1 shift Positive Edge Triggering

18 모바일컴퓨팅특강 18 Direct inputs Most flip-flops provide direct, or asynchronous, inputs that immediately sets or clears the state. The below is a D flip-flop with active-low direct inputs. Direct inputs to set or reset the flip-flop S’R’ = 11 for “normal” operation of the D flip-flop

19 모바일컴퓨팅특강 19 D FF with BDF Insert the symbol dff Edge-trigger symbol

20 모바일컴퓨팅특강 20 D FF with VHDL file

21 모바일컴퓨팅특강 21 FlipFlop with active-high Clock & asynchronous Clear library ieee; use ieee.std_logic_1164.all; entity dff_1 is port( d, clk, nclr : in std_logic; q : out std_logic ); end dff_1 ; architecture a of dff_1 is begin process(nclr,clk) begin if( nclr='0') then q <='0'; elsif(clk'event and clk='1') then q <= d; end if; end process; end a;

22 모바일컴퓨팅특강 22 FlipFlop with active- low Clock & asynchronous Clear library ieee; use ieee.std_logic_1164.all; entity dff_fall_1 is port( d, clk, nclr : in std_logic; q : out std_logic ); end dff_fall_1 ; architecture a of dff_fall_1 is begin process(nclr,clk) begin if( nclr='0') then q <='0'; elsif(clk'event and clk=‘0') then q <= d; end if; end process; end a;

23 모바일컴퓨팅특강 23 FlipFlop with active-high Clock & asynchronous Preset library ieee; use ieee.std_logic_1164.all; entity dff_ preset_1 is port( d, clk, npre : in std_logic; q : out std_logic ); end dff_ preset_1 ; architecture a of dff_ preset_1 is begin process(npre,clk) begin if( npre='0') then q <=‘1'; elsif(clk'event and clk=‘1') then q <= d; end if; end process; end a;

24 모바일컴퓨팅특강 24 FlipFlop with active-high Clock & asynchronous Clear & Preset library ieee; use ieee.std_logic_1164.all; entity dff_ presetclr_1 is port( d, clk, npre,nclr : in std_logic; q : out std_logic ); end dff_ presetclr_1 ; architecture a of dff_ presetclr_1 is begin process(npre, nclr, clk) begin if( npre='0') then q <=‘1'; elsif( nclr='0') then q <=‘0'; elsif(clk'event and clk=‘1') then q <= d; end if; end process; end a;

25 모바일컴퓨팅특강 25 Shift Register library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shiftreg is port( d, clk,nclr : in std_logic; qa,qb : out std_logic ); end shiftreg; architecture a of shiftreg is signal tqa,tqb : std_logic; begin process(nclr,clk) begin if( nclr='0') then tqa <='0'; tqb <='0'; elsif(clk'event and clk='1') then tqa <= d; tqb <= tqa; end if; end process; qa<=tqa; qb<=tqb; end a;

26 모바일컴퓨팅특강 26 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt161_4bits is port( d3,d2,d1,d0 : in std_logic; nld,ent,enp : in std_logic; clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic; rco : out std_logic); end cnt161_4bits; architecture a of cnt161_4bits is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) variable d : std_logic_vector(3 downto 0); begin d := d3&d2&d1&d0; if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if(nld='0') then q <= d; elsif(ent='1' and enp='1') then q <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); rco <= ent and q(3) and q(2) and q(1) and q(0); end a; 74161 은 실제로 가장 널리 사용되는 4 비트 카운터임 4 bits Universal Counter: 74161

27 모바일컴퓨팅특강 27 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod16cnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod16cnt; architecture a of mod16cnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then q <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; Modulo 16 Up Counter

28 모바일컴퓨팅특강 28 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod16dncnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod16dncnt; architecture a of mod16dncnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then q <= q-'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; Modulo 16 Down Counter

29 모바일컴퓨팅특강 29 Modulo 16 Up Down counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity UpDncnt4 is port( clk,nclr: in std_logic; UpDn: in std_logic; q3,q2,q1,q0 : out std_logic); end UpDncnt4; architecture a of UpDncnt4 is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if( UpDn='1') then q <= q+'1'; else q <= q-'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; 1 이 면 증 가 0 이면 감소

30 모바일컴퓨팅특강 30 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod15cnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod15cnt; architecture a of mod15cnt is signal q : std_logic_vector( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if( q="1110") then q<="0000"; elseq <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; 14 에서 0 으로 증가 Modulo 15 Up Counter

31 모바일컴퓨팅특강 31 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod15holdcnt is port( clk,nclr: in std_logic; q3,q2,q1,q0 : out std_logic); end mod15holdcnt; architecture a of mod15holdcnt is signal q : std_logic_vector ( 3 downto 0); begin process(nclr,clk) begin if( nclr='0') then q <="0000"; elsif(clk'event and clk='1') then if( q=14) thenq<=q; else q <= q+'1'; end if; end process; q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); end a; 14 에서 정지 0-14 hold Up Counter

32 모바일컴퓨팅특강 32 1bit Async load down counter

33 모바일컴퓨팅특강 33 4bit Async load down counter

34 모바일컴퓨팅특강 34 1bit Async Sync load down counter

35 모바일컴퓨팅특강 35 8bit Async sync load down counter

36 모바일컴퓨팅특강 36 State Machine - 강의순서 Mealy Machine Moore Machine

37 모바일컴퓨팅특강 37 State Machine - Mealy Machine Mealy Machine 현재의 상태 (Current State) 와 현재의 입력 (Inputs) 에 의해 출력이 결정 Combination Logic F/F Inputs Outputs Current State Combination Logic Next State

38 모바일컴퓨팅특강 38 State Machine - Moore Machine Moore Machine 현재의 상태 (Current State) 에 의해 출력 (Outputs) 이 결정 Combination Logic F/F Inputs Outputs Current State Combination Logic Next State

39 모바일컴퓨팅특강 39 Mealy Machine – VHDL Example S0 S1 0/00 1/00 0/01 1/10 WindowAct / RiseShot, FallShot 입력 / 출력 1, 출력 2 해석 1. WindowAct 신호가 0 에서 1 로 변하는 순 간에 RiseShot 을 1 로 만들고, 2. WindowAct 신호가 1 에서 0 로 변하는 순 간에 FallShot 을 1 로 만들어야함.. 해석 1. WindowAct 신호가 0 에서 1 로 변하는 순 간에 RiseShot 을 1 로 만들고, 2. WindowAct 신호가 1 에서 0 로 변하는 순 간에 FallShot 을 1 로 만들어야함..

40 모바일컴퓨팅특강 40 Mealy Machine– Process 2 개 사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY RiseFallShot IS PORT(clk: INSTD_LOGIC; reset: INSTD_LOGIC; WindowAct: INSTD_LOGIC; RiseShot, FallShot : OUTSTD_LOGIC); END RiseFallShot; ARCHITECTURE a OF RiseFallShot IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSEstate <= s0; END IF; WHEN others => IF WindowAct='0' THENstate <= s0; ELSEstate <= s1; END IF; END CASE; END IF; END PROCESS; Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분 Entity 문에 입 출력이 표시.

41 모바일컴퓨팅특강 41 Mealy Machine– Process 2 개 사용 PROCESS(state, WindowAct) BEGIN if( state= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( state= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; END PROCESS; END a; Combination Logic F/F Outputs Current State Combination Logic Next State Inputs 같은 부분

42 모바일컴퓨팅특강 42 Mealy Machine– Process 3 개 사용 library ieee; Use ieee.std_logic_1164.all; ENTITY RiseFallShot_v2 IS PORT( clk: INSTD_LOGIC; reset: INSTD_LOGIC; WindowAct: INSTD_LOGIC; RiseShot, FallShot: OUTSTD_LOGIC); END RiseFallShot_v2; ARCHITECTURE a OF RiseFallShot_v2 IS TYPE STATE_TYPE IS (s0, s1); SIGNAL State, NextState: STATE_TYPE; BEGIN PROCESS (State, WindowAct) BEGIN CASE State IS WHEN s0 => IF WindowAct='1' THEN NextState <= s1; ELSE NextState <= s0; END IF; WHEN others => IF WindowAct='0' THEN NextState <= s0; ELSE NextState <= s1; END IF; END CASE; END PROCESS; Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분 Entity 문에 입 출력이 표시.

43 모바일컴퓨팅특강 43 Mealy Machine– Process 3 개 사용 PROCESS(reset,clk) BEGIN IF reset = '0' THEN State <= s0; ELSIF clk'EVENT AND clk = '1' THEN State <= NextState; END IF; END PROCESS; PROCESS(State,WindowAct) BEGIN if( State= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( State= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; END PROCESS; END a; Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분

44 모바일컴퓨팅특강 44 Moore Machine – VHDL Example S0 000 S1 010 0 0 1 1 S2 101 1 상태 출력 입력 : WindowAct 출력 : y(2:0) 해석 1. WindowAct 신호가 0 에서는 상태의 변화가 없으며, 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다. 2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “000” 을 S1 인 경우에는 “010” 을 S2 인 경우에는 “101” 을 출력한다. 해석 1. WindowAct 신호가 0 에서는 상태의 변화가 없으며, 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다. 2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “000” 을 S1 인 경우에는 “010” 을 S2 인 경우에는 “101” 을 출력한다.

45 모바일컴퓨팅특강 45 Moore Machine– Process 2 개 사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY MooreMachine IS PORT(clk: INSTD_LOGIC; reset: INSTD_LOGIC; WindowAct: INSTD_LOGIC; y : OUTSTD_LOGIC_vector(2 downto 0)); END MooreMachine; ARCHITECTURE a OF MooreMachine IS TYPE STATE_TYPE IS (s0, s1,s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSE state <= s0; END IF; WHEN s1 => IF WindowAct='1' THEN state <= s2; ELSE state <= s1; END IF; WHEN others => IF WindowAct='1' THEN state <= s0; ELSE state <= s2; END IF; END CASE; END IF; END PROCESS; Entity 문에 입 출력이 표시. Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분 같은 부분

46 모바일컴퓨팅특강 46 Moore Machine– Process 2 개 사용 PROCESS(state) BEGIN CASE state IS WHEN s0 => y <= "000"; WHEN s1 => y <= "010"; WHEN others => y <= "101"; END CASE; END PROCESS; END a; Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부 분

47 모바일컴퓨팅특강 47 Moore Machine– Process 3 개 사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY MooreMachine_v3 IS PORT(clk: INSTD_LOGIC; reset: INSTD_LOGIC; WindowAct: INSTD_LOGIC; y : OUTSTD_LOGIC_vector(2 downto 0)); END MooreMachine_v3; ARCHITECTURE a OF MooreMachine_v3 IS TYPE STATE_TYPE IS (s0, s1,s2); SIGNAL state, NextState: STATE_TYPE; BEGIN PROCESS ( State, WindowAct) BEGIN CASE State IS WHEN s0 => IF WindowAct='1' THEN NextState <= s1; ELSE NextState <= s0; END IF; WHEN s1 => IF WindowAct='1' THEN NextState <= s2; ELSE NextState <= s1; END IF; WHEN others => IF WindowAct='1' THEN NextState <= s0; ELSE NextState <= s2; END IF; END CASE; END PROCESS; Entity 문에 입 출력이 표시. Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분

48 모바일컴퓨팅특강 48 Moore Machine– Process 3 개 사용 PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN state <= NextState; END IF; END PROCESS; PROCESS(state) BEGIN CASE state IS WHEN s0 => y <= "000"; WHEN s1 => y <= "010"; WHEN others => y <= "101"; END CASE; END PROCESS; END a; Combination Logic F/F Inputs Outputs Current State Combination Logic Next State 같은 부분 같은 부분 같은 부분 같은 부분

49 모바일컴퓨팅특강 49 참고문헌 1. PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE. 2. FLOYD, DIGITAL FUNDAMENTALS WITH VHDL. 3. ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS. 4. SKHILL, VHDL FOR PROGRAMMABLE LOGIC. 5. PELLERIN, VHDL MADE EASY. 6. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.

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