1 CPLD 簡介 2011/01/16 v1.0 By Johnson Chang

2 What is CPLD Complex Programmable Logic Device Complex Programmable Logic Device Your own ASIC ( Application Specified Integrated Circuit) Your own ASIC ( Application Specified Integrated Circuit) Logic Design  Implementation with Logic Design  Implementation with 1. Standard TTL / COMS 2. CPLD / FPGA

3 Why CPLD? Large Digital Logic Design is possible Large Digital Logic Design is possible Minimize PCB size Minimize PCB size High Speed ( 3/4/5 nS vs 18nS ) High Speed ( 3/4/5 nS vs 18nS ) Security Security

4 CPLD TTL

5 How to design CPLD Xilinx / Altera Xilinx / Altera Altera Quartus / Maxplux II (phase out) Altera Quartus / Maxplux II (phase out) Block Diagram Schematic ( bdf ) / VHDL / Verilog Block Diagram Schematic ( bdf ) / VHDL / Verilog

6 Study Sequence Quartus Installation Quartus Installation Example Demonstration Example Demonstration Introduction of Terasic CPLD Kit Introduction of Terasic CPLD Kit Programming Example Programming Example Implement 74LS138 with 3 SW input Implement 74LS138 with 3 SW input Implement 74LS138 with 2Hz input Implement 74LS138 with 2Hz input Design a 7-Segment decoder Design a 7-Segment decoder Design a 4*7 7-Segment decoder Design a 4*7 7-Segment decoder Design a 4-byte RAM Design a 4-byte RAM Design a counter 1,3,5,7,1,3,5,7 、、、 Design a counter 1,3,5,7,1,3,5,7 、、、

7 Learning Material 陳慶逸的教學網站 陳慶逸的教學網站 陳慶逸的教學網站 CPLD/FPGA 數位電路教學與設計資源 CPLD/FPGA 數位電路教學與設計資源 CPLD/FPGA 數位電路教學與設計資源 CPLD/FPGA 數位電路教學與設計資源 張正賢教學網站 張正賢教學網站 張正賢教學網站