1. Synchronous Sequential Circuit Design Digital Clock Design

2. 3-bit binary ripple asynchronous counter William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3. The 3-bit binary ripple counter waveforms William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

4. 3-bit binary ripple counter state diagram William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

5. propagation delay on ripple counter outputs William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

6. Block diagram for a digital clock William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. The Lab. Use synchronous sequential circuit to implement a digital clock