1. Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

2. Terminology PLD – Programmable Logic Device –IC that contains 1000’s of undefined logic devices

3. PLDs Thousands of basic logic gates Advanced sequential functions Single package Not yet configured to perform a function Limited only by number of input & output pins Some versions are erasable & reprogrammable Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

4. Figure 4–1 Sample PLDs: (a) Altera EPM7128S; (b) Xilinx XC95108. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

5. PLD Design Flow CAD to draw the schematic Schematic Capture to convert to binary file Program to alter PLD internal connections VHDL - Very High Speed Integrated Circuit Hardware Description Language –Programming Language similar to C++

6. Figure 4-2 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

7. PLD Design Flow Implementing X=AB + B + C –Using 7400 series ICs –Using a PLD Altera Corporation tools –MAX+PLUS II (entry-intermediate level) –Quartus II (more advanced) –UP-1 or UP-2 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

8. Figure 4–3 Implementing the equation X = AB + B + C using 7400-series logic ICs: (a) logic diagram; (b) connections to IC chips. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. (a) _ ___

9. Figure 4–3 (continued) Implementing the equation X = AB + B + C using 7400-series logic ICs: (a) logic diagram; (b) connections to IC chips. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. (b) _ ___

10. Figure 4–4 Implementing the equation X = AB + B + C using a PLD. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. _ ___

11. PLD Architecture SPLDs –most basic –least expensive –configurable logic gates –programmable interconnection points –may have memory flip-flops –typically 16 inputs and 8 outputs –product terms from AND gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

12. Figure 4–6 One-line convention for PLDs. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

13. PLD Architecture PALs –programmable array logic –gives Sum-of-Products form –uses OR gate

14. Figure 4–7 PAL architecture of an SPLD. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

15. PLD Architecture PLAs –programmable logic array –uses programmable OR gates

16. Figure 4–8 PLA architecture of an SPLD. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

17. PLD Architecture Flip-flop memory section –Used in sequential logic –Form of digital memory Data steering circuitry –Directs inputs and outputs to their proper destinations

18. PLD Architecture PAL16L8 is a typical PAL device –16 indicates 16 inputs –8 indicates 8 outputs –L means outputs are active LOW Output goes LOW when active Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

20. PLD Architecture CPLDs –complex programmable logic devices –combine several PAL-type SPLDs into single package Each structure called a macrocell –non-volatile –repeatedly programmed

21. Figure 4–10 Internal structure of a CPLD. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

22. PLD Architecture FPGAs –field-programmable gate arrays –uses a look-up-table Truth table that lists all possible inputs with their desired response –more dense than CPLD –memory is volatile Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

23. Figure 4-11 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

24. Summary Programmable Logic Devices can be used to replace 7400-series and 4000-series ICs. They contain the equivalent of thousands of logic gates. Computer-Aided Design (CAD) tools are used to configure them to implement the desired logic. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

25. Summary The two most common methods of PLD design entry are graphic entry and VHDL entry. To use graphic entry the designer uses CAD tools to draw the logic that needs to be implemented. To use VHDL entry the designer uses a text editor to write program descriptions defining the logic to be implemented Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

26. Summary PLD design software usually includes a logic simulator. This feature allows the user to simulate levels to be input to the PLD and shows the output simulation to those input conditions. Most PLDs are erasable and re-programmable. This allows the user to test many versions of their logic design without ever changing ICs. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

27. Summary Basically there are three types of PLDs: SPLDs, CPLDs and FPGAs. SPLDs consist of several multi-input AND gates feeding the inputs to OR gates and memory flip- flops. The CPLD consists of several interconnected SPLDs. The FPGA is the most dense form of PLD. It solves its logic using a look-up table to determine the desired output. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version