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第10章 移位暫存器 10-1 移位暫存器的基本功能 10-2 串列輸入/輸出移位暫存器 10-3 其他移位暫存器的線路型態
10-1 移位暫存器的基本功能 10-2 串列輸入/輸出移位暫存器 10-3 其他移位暫存器的線路型態 10-4 移位暫存器計數器 10-5 移位暫存器的應用
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Figure 10--1 The flip-flop as a storage element.
10-1 移位暫存器的基本功能 Figure The flip-flop as a storage element. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-1 移位暫存器的基本功能 Figure Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.) Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--3 Serial in/serial out shift register.
10-2 串列輸入/輸出移位暫存器 Figure Serial in/serial out shift register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-2 串列輸入/輸出移位暫存器 Figure Four bits (1010) being entered serially into the register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-2 串列輸入/輸出移位暫存器 Figure Four bits (1010) being serially shifted out of the register and replaced by all zeros.
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Figure 10--6 Open file F10-06 to verify the operation.
10-2 串列輸入/輸出移位暫存器 例題10-1 根據圖10-6(a)指定的輸入資料與時脈脈波，試畫出五位元暫存器的位元狀態。 Figure Open file F10-06 to verify the operation. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-2 串列輸入/輸出移位暫存器 Figure Logic symbol for an 8-bit serial in/serial out shift register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--8 A serial in/parallel out shift register.
10-3 其他移位暫存器的線路型態 Figure A serial in/parallel out shift register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-3 其他移位暫存器的線路型態 例題10-2 根據圖10-9(a) 輸入資料與時脈脈波，畫出4位元暫存器的狀態。
10-3 其他移位暫存器的線路型態 例題10-2 根據圖10-9(a) 輸入資料與時脈脈波，畫出4位元暫存器的狀態。 Figure 10—9 4位元暫存器的狀態 Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-3 其他移位暫存器的線路型態 Figure A 4-bit parallel in/serial out shift register. Open file F10-10 to verify the operation. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-3 其他移位暫存器的線路型態 例題10-3 試根據圖10-11(a) 的並列輸入資料、時脈與SHIFT /LOAD 的波形，畫出4位元暫存器的資料輸出波形。 Figure Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--12 A parallel in/parallel out register.
10-3 其他移位暫存器的線路型態 Figure A parallel in/parallel out register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-3 其他移位暫存器的線路型態 Figure Four-bit bidirectional shift register. Open file F10-13 to verify the operation. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-3 其他移位暫存器的線路型態 例題10-4 試根據圖10-14(a) 中控制輸入RIGHT /LEFT 的波形，求出再每一個時脈脈波之後，圖10-13移位戰存器的狀態。假設Q0=1、Q1=1、Q2=0、Q3=1，而且串列資料輸入為LOW狀態。 Figure Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--15 4-bit and 5-bit Johnson counters.
10-4 移位暫存器計數器 Figure bit and 5-bit Johnson counters. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--16 Timing sequence for a 4-bit Johnson counter.
10-4 移位暫存器計數器 Figure Timing sequence for a 4-bit Johnson counter. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--17 Timing sequence for a 5-bit Johnson counter.
10-4 移位暫存器計數器 Figure Timing sequence for a 5-bit Johnson counter. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-4 移位暫存器計數器 Figure A 10-bit ring counter. Open file F10-18 to verify the operation. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-4 移位暫存器計數器 例題10-5 如果有一個類似據圖10-18的環狀計數器，它的初始狀態為 ，試畫出每一個輸出端Q的波形。 Figure Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--20 The shift register as a time-delay device.
10-5 移位暫存器的應用 Figure The shift register as a time-delay device. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-5 移位暫存器的應用 例題10-6 試計算圖10-21中，在串列輸入端與每一個輸出端之間延遲時間。並繪出時序圖說明。
10-5 移位暫存器的應用 例題10-6 試計算圖10-21中，在串列輸入端與每一個輸出端之間延遲時間。並繪出時序圖說明。 Figure Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-5 移位暫存器的應用 Figure Timing diagram showing time delays for the register in Figure Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--23 A shift register connected as a ring counter.
10-5 移位暫存器的應用 Figure A shift register connected as a ring counter. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-5 移位暫存器的應用 Figure Timing diagram showing two complete cycles of the ring counter in Figure when it is initially preset to 1000. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-5 移位暫存器的應用 Figure Simplified logic diagram of a serial-to-parallel converter. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--26 Serial data format.
10-5 移位暫存器的應用 Figure Serial data format. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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10-5 移位暫存器的應用 Figure Timing diagram illustrating the operation of the serial-to-parallel data converter in Figure
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Figure 10--28 UART interface.
10-5 移位暫存器的應用 Figure UART interface. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--29 Basic UART block diagram.
10-5 移位暫存器的應用 Figure Basic UART block diagram. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--30 Simplified keyboard encoding circuit.
10-5 移位暫存器的應用 Figure Simplified keyboard encoding circuit.
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Figure 10--31 Sample test pattern.
10-5 移位暫存器的應用 Figure Sample test pattern. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--32 Basic test setup for the serial-to-parallel data converter of Figure 10-25.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure Proper outputs for the circuit under test in Figure The input test pattern is shown. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--34 Logic symbol for the 74HC164.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--35 Logic symbol for the 74HC194.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--36 An n-bit serial in/serial out shift register.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--37 Serial in/serial out shift register simulation waveform.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--38 Serial in/parallel out shift register.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure Typical combinational SHIFT/ logic for one D input of a parallel in/serial out shift register. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--40 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--41 Bidirectional shift register.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--42 Output waveform for a 4-bit bidirectional shift register.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--43 Timing sequence simulation for the 4-bit Johnson counter.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--44 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--45 Timing sequence simulation for the 4-bit ring counter.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--46 Basic logic diagram of the security entry system.
Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--47 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--48 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--49 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--50 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--51 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--52 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--53 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--54 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--55 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--56 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--57 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--58 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--59 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--60 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--61 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--62 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--63 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--64 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--65 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--66 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--67 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--68 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--69 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--70 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--71 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--72 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--73 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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Figure 10--74 Thomas L. Floyd Digital Fundamentals with VHDL
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.
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