TALK, LKr readout and the rest… R. Fantechi, G. Lamanna 15/12/2010

TALK board TALK trigger interface The main function of the TALK (Trigger Adaptor for LKr) board is to provide a trigger interface to use the LKr with the SLM system The SLM+CPD system has two problems from Trigger point of view: distribution distribution of the trigger signal to the boards timestamping timestamping of the events doughter board The TALK board is a TEL62/TELL1 doughter board: TTC TTC receiver is the same as for the other systems Same timestamp synchronization as for the other systems Same board control and firmware Additional functionality provided both for LKr and other systems: Calibration Calibration control board L0TP receiver L0TP receiver (prototype) Interface board Interface board for non-TEL62 based systems standalone Possible to use it in “standalone” mode: without TEL62/TELL1, either in a box or on a support card in a VME crate

Board description Connectors Connectors : 2xTEL62, 1xPower, 5xGigabit, 11xLemo, 4xRJ11, 1xLTU, JTAG, I2C TAXI TAXI chip Cyclone3 FPGA Altera Cyclone3: EPC3C120F780C7 Level converters Power: the +5V,-5V,+2.5V are provided by the connector on the TEL62 1.2V and 3.3V generated in the card 6U frame Possibility to reuse the card in a 6U frame, providing the correct power and, eventually, the VME interface

Trigger interface for LKr TAXI chip The trigger distribution was based on the asynchronous TAXI chip DC The timestamp was attached to the data in the DC (the timestamp was not propagated in the CPD) “regenerated” synchronously In the NA62 L0 trigger the timestamp will be not propagated through TTC, but are “regenerated” synchronously (same reset) in each TEL62 (and in L0TP) interface TTCTAXI timestamp lists The TALK board will provide the interface between TTC and TAXI distribution system and the production of the timestamp lists to be merged in the readout PC PP SL TTC TAXI TALK FPGA To CPD ETH 5: to R/O PC

Calibration The components of the NA48 LKr calibration system – DAC, pulsers and switches mounted directly on the flanges Setup and selection done with CAMAC out registers (open coll.) – NIM electronics to setup the pulse sequences Async/sync wrt experiment clock In burst and/or out burst or continuous Different rates in burst/out burst Multiple outputs for pulser, TS, PMB – CAMAC modules See first item Control of the NIM logic Programmable delay for clock sync pulses: time scan possible NIM/CAMAC Hardware is old, future support still not clear – Possible upgrade VME output registers from the old NA48 slow control, many available Programmable logic to handle the NIM and part of the CAMAC setup – TALK board

Calibration with the TALK card We are designing the hardware and firmware of the TALK board to be able to use it also for this job – Availability of NIM input and output Burst signals, clock input, pulser outputs – Implementation of a delay line for time scans – Use one Ethernet link to configure the calibration setup In burst/out burst logic Pulse frequencies Operational modes It can be used for calibration either on a TEL62 or standalone – In the first case the clock is coming internally – In the second case it could sit in a box or on a support PCB in a VME crate to get the power. Clock via NIM input Easy to interface with L0TP – If L0TP will be the TALK (or a TALK2), calibration triggers are sent internally to it – Otherwise a NIM output will provide a signal to the L0TP front panel It could also be possible to define this instance of the TALK board as “pseudo detector” and send trigger primitives via Ethernet as the other detectors I.e. it can be used as a primitive generator for random triggers Or to generate primitives for any pulser-type signal

First draft firmware schematics

Trigger interface for other detectors not directly based on TEL62TTC system The TALK board should be used to distribute trigger in systems not directly based on TEL62 and without TTC system TTC NIM/TTL, LVDS DATA DATA with TIMESTAMP FRONT END ? ? define outputs and inputs Feedback from potential users in order to define outputs and inputs (for instance the LVDS output in the sketch above isn’t present) The firmware both in the TALK FPGA and PP/SL should be adapted TALK TEL62

Board control Three way to control the board: CCPC CCPC: using and adapted TDSPY version, through the TEL62 firmware I2C I2C: external connector or TEL62 GLUE card controller Direct Ethernet Direct Ethernet: in the SLM style, using commands decoded at firmware level CCPCPP GLUE TALK FPGA I2C PP reg Direct Eth

L0TP prototype 4 Ethernet connectors 4 different subsystem 4 Ethernet connectors will be used to receive trigger primitives from 4 different subsystem in order to test the TEL62 capability as L0TP We use “MoreThanIp” IP core for gigabit control Resources needed for each core: max 4400 LE max 4400 LE ( in Cyclone III) max 2500 Ram bits max 2500 Ram bits (3888 kBits in Cyclone III) around 20 pins around 20 pins (531 in Cyclone III) TALK FPGA two PPs The L0TP algorithms will be implemented on PPs: the TALK FPGA is connected to two PPs TALK FPGA The TALK FPGA will manage the connection with the LTU and, eventually, the resynchronization. Four RJ11 choke/error Four RJ11 connectors will manage the inputs for choke/error from the detectors

L0TP prototype in synchro run TELL1 + Taxi Board LT U + TT Cex LKrCHOD SAC RICHSTRAW S GTK Small Scintillat or TEL62 CUS TOM SLM CUS TOM Trigger primit. TTC to LTU Trigger to SLM

Status Schematic board design Schematic board design quite advanced: selected and placed All components selected and placed All logic blocks done Recheck powers and connections Capacitors net and LTU Capacitors net and LTU connector still missed gigabit controller firmware Almost completed gigabit controller firmware: Input/output pins definition for PP and LTU interconnection missed calibration Almost completed calibration logic blocs preliminary version The firmware isn’t the final one: preliminary version to define the FPGA requirements and the pinout There is still room and time for changes and request Internal Note in preparation: will be completed before the prototype realization

Prospects Schematics Schematics will be ready soon CERN PCB workshop Routing to be done CERN PCB workshop (which is doing TEL62) PCB production and mounting PCB production and mounting of prototype will be done in spring TEL62 firmware TEL62 firmware: Based on the standard TEL62 firmware: Trigger information preparation for TAXI L0TP: trigger logic Control: register definition Problems with HDL designer will be investigated TALK-FPGA firmware TALK-FPGA firmware: Gigabit receiver and transmitter Direct ethernet connection Calibration logic L0TP: choke/error receiver L0TP: resynchronization and LTU connection L1/2 trigger interface Lemo input/output

Status of the CREAM readout Market Survey Highly qualified

Schedule

Crate layout Improvements in the definition of connectors: Readout and trigger sums on the front Choke,error on P0 Test inputs on the board side Choke and error lines Propagated on P0 to the control board Then Or-ed to a connector/crate Need a final mux