Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.
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Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans
Uli Schäfer 2 JEM1.0 status 4 main boards available All fully populated with input modules 3 working. 4th module: shorts on one daughter connector (TTCdec) SystemACE configurator required some tuning (clock signal integrity) Readout modules available for all JEMs (HDMP1032, SFP or SFF dual transmitter) 1 TLK1201A-based readout module available Firmware (sum, input) stable - old readout format firmware needs to be modified for 9U ROD format
Uli Schäfer 3 JEM1.0 status : tests JEM tests done in Mainz, at RAL and CERN test beam Up to 3 JEMs in a 9U crate allowing for FIO tests either direction, along with VMM, TCM, CMM (and CPMs!) External data sources for LVDS : 1 DSS 16-channel (MZ) Several DSS (RAL) LSM (RAL) PPR (RAL, CERN - 4 channels) External data sinks for Merger signals : 2 CMMs (RAL) Readout path: Complete ROS (RAL, CERN) G-link tester with f/w pattern comparison (MZ)
Uli Schäfer 4 JEM1.0 status : tests System tests at RAL: (from June 2004) DSS JEM crate CMM system CMM ROD ROS ROD ROS Comparing readout data against simulation. Data taken up to 5 slices of JEM DAQ data. Trigger rate up to 60kHz, 4*10 6 events analysed, no errors observed on JEM readout. Interface tests: LVDS inputs, merger outputs, FIO, readout links BER measured, no errors in 10 13 (CMM,FIO), 10 14 (ROD)*, 10 15 bits (LVDS) Latency within budget (< 9.5 ticks, Jet)
Uli Schäfer 5 FIO tests : delay scan All data latched into jet processor on a common clock edge Sweep TTCrx delay setting, 104ps steps Measure data errors on each channel : 10 bits, 5 signal lines Single channel 8ns error free All channels 6.5ns error free
Uli Schäfer 6 JEM1.0 tests : conclusion JEM1.0 successfully tested Algorithms All interfaces LVDS inputs (errors on PPR-JEM links) FIO inter-module links Merger out Optical readout to 6U RODs * VME CAN slow control *G-link data errors observed on ROI readout recently
Uli Schäfer 7 Readout module : G-link problems History : HDMP1022, driven by bunch clock : works Concerns about clock jitter temporary fix on JEM1.0: route VME clock (40MHz crystal clock) to G-links via sum FPGA (supply both PHY chips from same FPGA pin) : works Use HDMP1032, supply clock from ROCs (ie. ROI link supplied via jet FPGA) Initially no problems seen At RAL link errors observed when LVDS links active Problem confirmed in Mainz, even without LVDS activity Quick fix Link seems to be stable if clocked via sum FPGA Proper solution : generate clean crystal clock on readout module. Final version of readout module to be made a 4-layer PCB further tests required G-link issue should not affect JEM1.1 since it is a problem of RM only
Uli Schäfer 8 in production Identical to JEM 1.0 Additional daughter module: Control Module (CM) CAN VME control Fan-out of configuration lines Expected back from assembly soon JEM1.1
Uli Schäfer 9 Plans Re-design readout module : start now Further design work required JTAG test adapters Input modules (add voltage/temperature sensor) Control module Readout tests (9U RODs) Further tests with stress patterns required on all interfaces, particularly on FIOs Tests at elevated temperature Further LVDS tests required (LSM, PPR) PRR in May / June Production time ~8 weeks !!!! Lead time for FPGAs !!!!