1. The Data Handling Hybrid Igor Konorov TUM Physics Department E18

2. Overview DHH functionality Proposal for DHH architecture DHH location Alternative DHH architecture Others PXD-DAQ Workshop И.Коноров, TUM 25-26 September 2010 2

3. DHH functionality 1.Voltage regulators 2.Slow control: Provision of JTAG interface to configure PXD Provision of slow control interface to configure DHH cards Monitoring voltages, currents, temperature 3.CLOCK synthesis from COMMON clock and distribution 4.DAQ functionality –Synchronous distribution of TRIGGER, RESET(?), … signals –Data buffering : 4x1Gb/sec –Sub event building : merging 4 data blocks into one –Transmission of merged data to DAQ via high speed optical serial link 25-26 September 2010 PXD-DAQ Workshop И.Коноров, TUM 3

4. Proposal for DHH system architecture PXD-DAQ Workshop И.Коноров, TUM DH Hybrid DHH Controller Belle II Trigger FPGA USB, Ethernet RJ45 DHH design : FPGA(Lattice/Xilinx) Optical transceivers Power module DHH functions: Optical network: Trigger, DAQ, Control Power Giessen Box Power Supplies 25-26 September 2010 4

5. Why optical interfaces ? Optical interfaces more reliable than copper Fiber length almost unlimited No electrical connections PXD-DAQ Workshop И.Коноров, TUM 25-26 September 2010 5

6. DHH location First scenario: 2-3 m away In Dock Passive Patch Panel High neutron flux Too high SingleEventUpset rate Loss of configuration information Second(current) scenario 10 m away No radiation Patch panel –Passive ? –Active I: signal conditioner for Serial Links –Active II: radiation hard laser drivers and optical transceivers (GBT* components) PXD-DAQ Workshop И.Коноров, TUM 30-50 cm Kapton Flat cable 2 m Patch Panel 30-50 cm Kapton Flat cable 10 m Patch Panel GBT- Gigabit Bidirectional Trigger Data Link, CERN developments for LHC upgrade 25-26 September 2010 6

7. Alternative DHH architecture Belle Trigger group(KEK) proposed: trigger interface directly to DHH module Possible scenario: PXD-DAQ Workshop И.Коноров, TUM Belle II Trigger Box FPGA SFP RJ45 Ladder’s flat cable connector PIGGY-BACK Power Module POWER CONNECTOR JTAG Slow Control DAQ Slow Control Box Copper interfaces 25-26 September 2010 7

8. Compare architectures TUM architecture –Optical interfaces – no ground loops –One optical interface for Trigger and Slow control –One additional non standard module – DHH controller  PXD-DAQ Workshop И.Коноров, TUM Alternative architecture (KEK) –Copper interfaces – can be isolated?  –Two copper connectors for Trigger and Slow Control  –One additional Trigger Box – Belle II standard module –One additional Slow Control Box  + 3 – 2 = +1+ 1 – 5 = -4 25-26 September 2010 8

9. DHH cards Functions: –DHP triggering –Data buffering Only inside FPGA for a moment –Backpressure –Clock synthesis ? –JTAG distribution –Slow control 25-26 September 2010 PXD-DAQ Workshop И.Коноров, TUM 9

10. DHH controller Functions –Interface trigger –Clock synthesis ? –JTAG support by uBlaze controller –System Management Loading firmware to DHH cards Monitoring DHH data buffer status – feedback to Trigger –Slow control : T, V, I … 25-26 September 2010 PXD-DAQ Workshop И.Коноров, TUM 10

11. DHH  DHP DHH generates two clock signals –Frame clock: 508.87 MHz/10240 = 49.69 kHz (~20 μs period) –Switcher clock: 508.87 MHz * 5/32 = 79.5 MHz or 508.87 MHz * 3/20 = 76.3 MHz Convert pulsed trigger signal to level trigger signal 25-26 September 2010 PXD-DAQ Workshop И.Коноров, TUM Belle Trigger DHP Trigger 11 one frame HEADER TRAILER