Chapter 3 How transistors operate and form simple switches CMOS logic gates PLA, PAL, FPGA Basic electrical characteristics of logic circuits

Transistor Switches Logic Circuits are built with Transistors MOSFETs “A full treatment of transistor behavior is beyond the scope of this text” MOSFETs NMOS - nchannel PMOS – pchannel

NMOS vs PMOS x = "low" x = "high" x = "high" x = "low" (a) A simple switch controlled by the input x (a) A switch with the opposite behavior Gate Gate Source Drain Drain Source V Substrate (Body) DD Substrate (Body) (b) NMOS transistor (b) PMOS transistor V V G G V V V V S D S D (c) Simplified symbol for an NMOS transistor (c) Simplified symbol for a PMOS transistor

NMOS & PMOS in Logic Circuits V D V = 0 V V D D V G V = 0 V S Closed switch Open switch when V = V when V = 0 V G DD G (a) NMOS transistor V = V V V S DD DD DD V G V V V = V D D D DD Open switch Closed switch when V = V when V = 0 V G DD G (b) PMOS transistor

NMOS Inverter + 5 V - V R R V V V V (a) Circuit diagram DD R R + 5 V - V V f f V V x x (a) Circuit diagram (b) Simplified circuit diagram x f x f (c) Graphical symbols

NMOS NAND vs AND V V V x x f 1 V 1 1 1 1 1 1 (a) Circuit DD V V DD DD V f V f V x 1 A x x f 1 2 V x 1 1 V x x f 1 2 x 2 1 1 1 1 V x 2 1 1 1 1 1 1 1 (a) Circuit (b) Truth table (a) Circuit (b) Truth table x x 1 1 x x f f 1 1 x x f f 2 2 x x 2 2 (c) Graphical symbols (c) Graphical symbols

NOR and OR What would an OR gate look like?

SN7408 - QUADRUPLE 2-INPUT POSITIVE-AND GATES

What’s Wrong With this Picture? V DD R V f V x When Vx is high there is a constant current through R

Structure of an NMOS Circuit V DD V f V x 1 V x 2

Structure of a CMOS circuit

V DD T 1 V V x f T 2

Vf Vf = X1X2 = X1 + X2 Vf = X1X2 PUN = Vf PDN = Vf

f = X1 + X2X3

Types of Integrated Circuits Standard Logic Programmable Logic Custom Logic

7400 Series Standard Chips - random logic V DD 7404 7408 7432 x 1 x 2 x 3 f = x1x2 + x2x3

Standard Logic Seldom used – with exception of buffers SSI MSI LSI Earliest devices only a few logic gates/transistors MSI 10 to100 gates LSI Greater than MSI VLSI

PLDs – Programmable Logic Devices PLA – Programmable Logic Array PAL – Programmble Array Logic CPLD – Complex PLD FPGA – Field Programmable Gate Arrays Custom Chips ASIC – Application Specific Integrated Circuit Gate Arrays Memory } SPLDs

PLA – Programmable Logic Array Based on the idea that logic functions can be realized in SoP form “Modest” size circuits Inputs & Outputs of not more than 32

x x x Programmable connections OR plane P P P P AND plane f f 1 2 3 1 4 AND plane f f 1 2

f1 = x1x2 + x1x3 + x1x2x3 f2 = x1x2 + x1x2x3 + x1x2 x x x Programmable connections OR plane P 1 P 2 P 3 P 4 f1 = x1x2 + x1x3 + x1x2x3 AND plane f2 = x1x2 + x1x2x3 + x1x2 f f 1 2

x x x 1 2 3 OR plane P 1 P 2 P 3 P 4 AND plane f f 1 2

PAL – Programmble Array Logic PLA’s Programmable Fuses Fabrication difficult Fuses slow down circuit PALs Only AND plane is programmable OR plane is fixed “Modest” size circuits Inputs & Outputs of not more than 32

x x x 1 2 3 P 1 f 1 P 2 P 3 f 2 P 4 AND plane

PAL Macrocell Select Enable f 1 Flip-flop D Q Clock To AND plane

CPLD – Complex PLD Multiple Circuit blocks on a single chip Each circuit block similar to PAL or PLA Typical CPLDs 16 Macro cells in each PAL like block 5 to 20 inputs to each OR gate 2 to more than 100 PAL like blocks

Structure of a complex programmable logic device (CPLD). PAL-like PAL-like I/O block I/O block block block Interconnection wires PAL-like PAL-like I/O block I/O block block block Structure of a complex programmable logic device (CPLD).

Note how output pin can be used as an input pin but associated macrocell cannot be used – some CPLDs include additional wiring to get around this limitation A section of a CPLD

Equivalent Gates Two input NAND gate used as measure of circuit size SPLD, CPLD macrocell = 20 Equivalent Gates PAL with 8 Macrocells can hold circuit of about 160 EG CPLD with 500 macrocells can hold circuit of about 10,000 EG Today’s logic circuits demand circuits greater than 10,000 EG

Memory as Logic How Memory Works Supply address Get Data Address Data

Memory as Logic Consider an 8 location memory chip with one binary bit at each location How many bits to address a location? How many bits at each location? Address Data

Memory as Logic A2 A1 A0 Data 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 Address Data f= A2A1A0 + A2A1A0 What would you name this?

FPGA – Field Programmable Gate Arrays Quite different from SPLDs and CPLDs FPGAs don’t have AND or OR planes Logic blocks – most common are LUTs I/O blocks Interconnection wires Greater than 1M EG

x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1 x 3 A three-input LUT.

Inclusion of a flip-flop in an FPGA logic block. Out D Q Clock Select Flip-flop In 1 2 3 LUT Inclusion of a flip-flop in an FPGA logic block.

A section of a programmed FPGA.

Custom Chips, Standard Cells, & Gate Arrays Programmable switches Size issue Speed issue

Custom Chips Complete flexibility in transistor placement and connection Large design effort Large cost Large quantities

ASICs Application Specific Integrated Circuits Standard Cell Libraries Configurable connections

Gate Arrays Gates prefabricated Connections added later

In-System Programming vs ? Out of System Programming Compare Teensy++ to ATtiny261

Programming PALs & PLAs usually programmed out of systems CPLDs usually programmed via JTAG in-system FPGAs programmed via JTAG in-system PALs, PLAs, & CPLDs nonvolatile FPGAs volatile

Practical Aspects Transistor Operation Static Operation - Voltage Levels Dynamic Operation – Transition Times Power Dissipation

The current-voltage relationship in the NMOS transistor. I D Triode Saturation V – V GS T V DS The current-voltage relationship in the NMOS transistor.

V D V D V G V = 0 V S Open switch when V = 0 V G

V D V = 0 V D V G V = 0 V S Closed switch when V = V G DD

Logic Values as Voltage Levels VOH High Noise Margin VOH – VIH VIH VIL Low Noise Margin VIL - VOL VOL Logic Value 0

Dynamic Operation Ideal gates We don’t live in an Ideal World Switch immediately in response to a change in inputs Transition logic states in zero time We don’t live in an Ideal World

Propagation delay V DD Gnd x A 50% 90% 10% t r f Fall Time Rise Time

Power Dissipation Static power consumption Dynamic power consumption

Static Power Consumption V DD V DD T 1 R V V V x f f V T x 2

Dynamic Power Consumption V DD V I x D I D V V f f V x

Fan-in Fan-out Fan-in Fan-out Number of inputs to the gate No choice really Fan-out Number of inputs being driven Increase in capacitance slows down rise time Increase in load changes DC levels

Buffers Non-inverting Inverting Tri-state Tri-state buffers

Laboratory Preparation Reading Chapter 3 Laboratory Preparation None

Homework Problems For SN74HCT00N and MM74HCT00N Calculate Noise Margins Find rise and fall times Find propagation delay some datasheets show this as tt Compare the two datasheets