1. Implementation technology

2. Transistor Switches

3. NMOS

4. PMOS

6. NMOS

7. PMOS

8. NMOS Logic Gates

9. NOT

10. NAND

12. NOR

14. CMOS Logic Gates

15. AND

16. OR

18. CMOS NOT

19. CMOS NAND

20. CMOS NOR

21. CMOS AND

24. 7400

26. 74244

27. Programmable Logic Array

28. General structure of PLA

29. Gate level diagram of a PLA

38. A section of a programmed FPGA.

39. 3.7 Custom Chips, Standard Cells, and Gate Arrays The designer of a custom chip has complete flexibility to decide the size of the chip, 1.the number of transistors the chip contains; 2.the placement of each transistor on the chip; 3.the way the transistors are connected together.

40. layout The process of defining exactly where on the chip each transistor and wire is situated is called chip layout. 版面设计、布局布线

41. Figure 3.40 A section of two rows in a standard-cell chip.

42. Figure 3.41 A sea-of-gates gate array.

43. Figure 3.42 The logic function in the gate array of Figure 3.41.

44. 3.8 Practical Aspects robustness of logic circuits 逻辑电路的鲁棒性 signal propagation delays 传输延时 power dissipation 功耗 Polysilicon 多晶硅 Extremely small dimensions

45. MOSFET Fabrication and Behavior L channel length W channel width ON-Resistance 1K Voltage Level in Logic Gates Noise Margin 噪声容限

46. Power Dissipation in Logic Gates Static Power Dynamic Power

47. Fan-in and Fan-out Fan-in: the number of inputs to the gates Fan-out: the number of other gates that a specific gate drives

48. buffer A logic gate has to drive a large capacitive load Built with relatively large transistors

49. Transmission Gates 传输门 NMOS:passes 0 well and 1 poorly PMOS :passes 1 well and 0 poorly

50. Exclusive-OR Gates 异或门

51. Multiplexer Circuit

52. Implementation Details for … Programmable Switches SPLD—metal-alloy fuses 铝合金熔丝 melted not reversible